MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 436
![IC MCU 16BIT 128K FLASH 112-LQFP](/photos/12/21/122139/mc9s12hz128cal_sml.jpg)
MC9S12HZ128CAL
Manufacturer Part Number
MC9S12HZ128CAL
Description
IC MCU 16BIT 128K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12HZ128CAL.pdf
(692 pages)
Specifications of MC9S12HZ128CAL
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12HZ128CAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 14 Serial Peripheral Interface (SPIV3)
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease I
14.4.5
14.4.5.1
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and
MODFEN bit as shown in
The mode fault feature is disabled while SS output is enabled.
14.4.5.2
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see
this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit
decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and
the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and
MOSI pin in slave mode are not used by the SPI.
436
Bidirectional Mode
When SPE = 1
Normal Mode
SPC0 = 0
SPC0 = 1
Special Features
SS Output
Bidirectional Mode (MOSI or MISO)
Care must be taken when using the SS output feature in a multimaster
system because the mode fault feature is not available for detecting system
errors between masters.
Serial Out
Serial Out
Table
Serial In
Serial In
Table 14-9. Normal Mode and Bidirectional Mode
SPI
SPI
BaudRateDivisor
Figure 14-11. Baud Rate Divisor Equation
Master Mode MSTR = 1
14-3.
MC9S12HZ256 Data Sheet, Rev. 2.05
BIDIROE
=
NOTE
SPPR
MOMI
MOSI
MISO
+
1
DD
2
current.
SPR
Serial Out
Serial Out
+
Serial In
Serial In
SPI
SPI
1
Slave Mode MSTR = 0
BIDIROE
Freescale Semiconductor
Table
MOSI
MISO
SISO
14-9). In
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