MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 144

• Manufacturer Part Number: MC9S12HZ128CAL
• Description: IC MCU 16BIT 128K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128CAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.5.2
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
4.3.5.3
Read: Anytime. Write: Anytime.
This register configures port pins PS[7:4] and PS[2:0] as either input or output.
When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data
Direction Register bits have no effect.
When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data
Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0
input pin and the associated Data Direction Register bit has no effect.
If the SPI and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to control
the I/O direction of the associated pin.
144
DDRS[7:4]
DDRS[1:0]
Reset
Reset
Field
7:4
1:0
W
W
R
R
DDRS7
PTIS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port S Input Register (PTIS)
Port S Data Direction Register (DDRS)
u
0
7
7
= Reserved or Unimplemented
= Reserved or Unimplemented
DDRS6
PTIS6
u
0
6
6
Figure 4-32. Port S Data Direction Register (DDRS)
Figure 4-31. Port S Input Register (PTIS)
Table 4-23. DDRS Field Descriptions
DDRS5
PTIS5
MC9S12HZ256 Data Sheet, Rev. 2.05
u
0
5
5
DDRS4
PTIS4
u
0
4
4
Description
u = Unaffected by reset
0
0
0
0
3
3
0
0
0
0
2
2
DDRS1
Freescale Semiconductor
PTIS1
u
0
1
1
DDRS0
PTIS0
u
0
0
0