MC56F8322MFAE Freescale Semiconductor, MC56F8322MFAE Datasheet - Page 96

• Manufacturer Part Number: MC56F8322MFAE
• Description: IC DSP 16BIT 60MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8322MFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 40KB (20K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Cpu Family: 56F8xxx
• Device Core Size: 16b
• Frequency (max): 60MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 21
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.75/3.6V
• Operating Supply Voltage (min): 2.25/3V
• On-chip Adc: 2(3-chx12-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 4 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Proper implementation of Flash security requires that no access to the EOnCE port is provided when
security is enabled. The 56800E core has an input which disables reading of internal memory via the
JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security
bytes.
7.2.3
If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be
used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling
Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory
configuration (.cfg) files. Add, or uncomment the following configuration command:
unlock_flash_on_connect 1
For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual.
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to
control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control
the period of the clock used for timed events in the FM erase algorithm. This register must be set with
appropriate values before the lockout sequence can begin. Refer to the 56F8300 Peripheral User Manual
for more details on setting this register value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides
down the system clock for timed events, as illustrated in
PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV
must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD
Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific
equations for calculating the correct values.
Two examples of FM_CLKDIV calculations follow.
96
Flash Lockout Recovery
JTAG
SYS_CLK
Figure 7-1 JTAG to FM Connection for Lockout Recovery
2
FMCLKDIV
FMERASE
56F8322 Techncial Data, Rev. 16
clock
FMCLKD
input
7
Figure
Flash Memory
7
7-1. FM_CLKDIV[6] will map to the
DIVIDER
7
Freescale Semiconductor
Preliminary