MC56F8322MFAE Freescale Semiconductor, MC56F8322MFAE Datasheet - Page 115

• Manufacturer Part Number: MC56F8322MFAE
• Description: IC DSP 16BIT 60MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8322MFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 40KB (20K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Cpu Family: 56F8xxx
• Device Core Size: 16b
• Frequency (max): 60MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 21
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.75/3.6V
• Operating Supply Voltage (min): 2.25/3V
• On-chip Adc: 2(3-chx12-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 4 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.9 Serial Peripheral Interface (SPI) Timing
Freescale Semiconductor
Preliminary
1. Parameters listed are guaranteed by design.
Cycle time
Master
Slave
Enable lead time
Master
Slave
Enable lag time
Master
Slave
Clock (SCK) high time
Master
Slave
Clock (SCK) low time
Master
Slave
Data set up time required for inputs
Master
Slave
Data hold time required for inputs
Master
Slave
Access time (time to data active from high-impedance
state)
Slave
Disable time (hold time to high-impedance state)
Slave
Data Valid for outputs
Master
Slave (after enable edge)
Data invalid
Master
Slave
Rise time
Master
Slave
Fall time
Master
Slave
Characteristic
Table 10-18 SPI Timing
56F8322 Technical Data, Rev. 16
Symbol
t
t
t
t
ELG
t
t
t
ELD
t
t
CH
DS
DH
t
t
DV
t
CL
t
DI
C
A
D
R
F
16.67
17.6
Min
100
4.8
3.7
50
50
25
25
16
20
—
—
—
—
—
—
—
—
0
0
2
0
0
1
Max
15.2
20.4
11.5
10.0
4.5
9.7
9.0
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Serial Peripheral Interface (SPI) Timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10-11,
10-11,
10-11,
10-11,
10-11,
10-11,
10-11,
10-11,
See Figure
10-9, 10-10,
10-9, 10-10,
10-9, 10-10,
10-9, 10-10,
10-9, 10-10,
10-9, 10-10,
10-9, 10-10,
10-9, 10-10,
10-12
10-12
10-12
10-12
10-12
10-12
10-12
10-12
10-12
10-12
10-12
10-12
10-12
115