C8051F996-GM Silicon Laboratories Inc, C8051F996-GM Datasheet - Page 9
![IC MCU 8BIT 8KB FLASH 24QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051F996-GM
Manufacturer Part Number
C8051F996-GM
Description
IC MCU 8BIT 8KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F996-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1943-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F996-GM
Manufacturer:
SILICON
Quantity:
570
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Figure 7.3. CP0 Multiplexer Block Diagram.............................................................. 96
Figure 8.1. CS0 Block Diagram ................................................................................ 98
Figure 8.2. Auto-Scan Example.............................................................................. 101
Figure 8.3. CS0 Multiplexer Block Diagram............................................................ 116
Figure 9.1. CIP-51 Block Diagram.......................................................................... 118
Figure 10.1. C8051F99x-C8051F98x Memory Map ............................................... 127
Figure 10.2. Flash Program Memory Map.............................................................. 128
Figure 14.1. Flash Program Memory Map (8 kB and smaller devices) .................. 151
Figure 15.1. C8051F99x-C8051F98x Power Distribution....................................... 162
Figure 16.1. CRC0 Block Diagram ......................................................................... 170
Figure 16.2. Bit Reverse Register .......................................................................... 177
Figure 18.1. Reset Sources.................................................................................... 179
Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 180
Figure 19.1. Clocking Sources Block Diagram ....................................................... 186
Figure 19.2. 25 MHz External Crystal Example...................................................... 188
Figure 20.1. SmaRTClock Block Diagram.............................................................. 195
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 204
Figure 21.1. Port I/O Functional Block Diagram ..................................................... 213
Figure 21.2. Port I/O Cell Block Diagram ............................................................... 214
Figure 21.3. Peripheral Availability on Port I/O Pins............................................... 217
Figure 21.4. Crossbar Priority Decoder in Example Configuration
Figure 21.5. Crossbar Priority Decoder in Example Configuration
Figure 22.1. SMBus Block Diagram ....................................................................... 233
Figure 22.2. Typical SMBus Configuration ............................................................. 234
Figure 22.3. SMBus Transaction ............................................................................ 235
Figure 22.4. Typical SMBus SCL Generation......................................................... 238
Figure 22.5. Typical Master Write Sequence ......................................................... 247
Figure 22.6. Typical Master Read Sequence ......................................................... 248
Figure 22.7. Typical Slave Write Sequence ........................................................... 249
Figure 22.8. Typical Slave Read Sequence ........................................................... 250
Figure 23.1. UART0 Block Diagram ....................................................................... 255
Figure 23.2. UART0 Baud Rate Logic .................................................................... 256
Figure 23.3. UART Interconnect Diagram .............................................................. 257
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 257
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 258
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 259
Figure 24.1. SPI Block Diagram ............................................................................. 263
Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 265
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Figure 24.5. Master Mode Data/Clock Timing ........................................................ 268
(No Pins Skipped) .............................................................................. 218
Connection Diagram .......................................................................... 266
Connection Diagram .......................................................................... 265
(4 Pins Skipped) ................................................................................ 218
Rev. 1.0
C8051F99x-C8051F98x
9
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