C8051F996-GM Silicon Laboratories Inc, C8051F996-GM Datasheet - Page 164
![IC MCU 8BIT 8KB FLASH 24QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051F996-GM
Manufacturer Part Number
C8051F996-GM
Description
IC MCU 8BIT 8KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F996-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1943-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F996-GM
Manufacturer:
SILICON
Quantity:
570
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- Download datasheet (3Mb)
C8051F99x-C8051F98x
15.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci-
sion oscillator prior to entering Suspend Mode. All digital logic (timers, communication peripherals, inter-
rupts, CPU, etc.) stops functioning until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from Suspend Mode:
Note: Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wake-
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-
up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 kW
pullup resistor to VDD is recommend for RST to prevent noise glitches from waking the device.
15.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.7) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VDD pin (see Figure 15.1). Power to most digital logic on the
chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain pow-
ered in two-cell mode. Only the Comparators remain functional when the device enters Sleep Mode. All
other analog peripherals (CS0, ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering
Sleep Mode. The system clock source must be set to the low power internal oscillator or the precision
oscillator prior to entering Sleep Mode.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode.
GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specs in sleep mode as they have
in normal mode.
‘C8051F99x-C8051F98x devices support a wakeup request for external devices. Upon exit from sleep
mode, the wake-up request signal is driven low, allowing other devices in the system to wake up from their
low power modes.
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT does not fall
below V
resume code execution upon waking up from sleep mode.
164
CS0 End of Conversion or End of Scan
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
up flags. All flags will read back a value of '0' during the first two system clocks following a wake-up from
suspend mode.
POR
. The PC counter and all other volatile state information is preserved allowing the device to
Rev. 1.0
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