C8051F996-GM Silicon Laboratories Inc, C8051F996-GM Datasheet - Page 163
![IC MCU 8BIT 8KB FLASH 24QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051F996-GM
Manufacturer Part Number
C8051F996-GM
Description
IC MCU 8BIT 8KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F996-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1943-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F996-GM
Manufacturer:
SILICON
Quantity:
570
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15.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Note: To ensure the MCU enters a low power state upon entry into Idle Mode, the one-shot circuit should be enabled
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “18.6. PCA Watchdog Timer
Reset” on page 183 for more information on the use and configuration of the WDT.
15.3. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter stop mode as soon as the instruc-
tion that sets the bit completes execution. In stop mode the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop
mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
Stop mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or suspend
mode will provide more power savings if the MCU needs to be inactive for a long period of time.
Note: To ensure the MCU enters a low power state upon entry into Stop Mode, the one-shot circuit should be enabled
by clearing the BYPASS bit (FLSCL.6).
by clearing the BYPASS bit (FLSCL.6).
Rev. 1.0
C8051F99x-C8051F98x
163
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