ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 93
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ST72F521M9T6
Manufacturer Part Number
ST72F521M9T6
Description
IC MCU 8BIT 60K FLASH 80-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F521M9T6.pdf
(215 pages)
Specifications of ST72F521M9T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8244
ST72F521M9T6
ST72F521M9T6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F521M9T6
Manufacturer:
ST
Quantity:
37 800
Company:
Part Number:
ST72F521M9T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST72F521M9T6TR
Manufacturer:
STMicroelectronics
Quantity:
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 57. Data Clock Timing Diagram
(from slave)
(from slave)
57).
(to slave)
(to slave)
(from master)
(from master)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
MOSI
SS
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
MSBit
MSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
CPHA =0
CPHA =1
Bit 4
Bit 4
Bit 4
Bit 4
Figure
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit3
Bit3
Bit3
Bit3
57, shows an SPI transfer with the four
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
ST72F521, ST72521B
LSBit
LSBit
LSBit
LSBit
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