ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 137
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ST72F521M9T6
Manufacturer Part Number
ST72F521M9T6
Description
IC MCU 8BIT 60K FLASH 80-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F521M9T6.pdf
(215 pages)
Specifications of ST72F521M9T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8244
ST72F521M9T6
ST72F521M9T6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ST72F521M9T6
Manufacturer:
ST
Quantity:
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Company:
Part Number:
ST72F521M9T6
Manufacturer:
STMicroelectronics
Quantity:
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CONTROLLER AREA NETWORK (Cont’d)
INTERRUPT CONTROL REGISTER (ICR)
Read/Write
Reset Value: 00h
Bit 7 = Reserved.
Bit 6 = ESCI Extended Status Change Interrupt
−
Set by software to specify that SCIF is to be set on
receive errors also.
Cleared by software to set SCIF only on status
changes and wake-up but not on all receive errors.
Bit 5 = RXIE Receive Interrupt Enable
−
Set by software to enable an interrupt request
whenever a message has been received free of er-
rors.
Cleared by software to disable receive interrupt re-
quests.
Bit 4 = TXIE Transmit Interrupt Enable
−
Set by software to enable an interrupt request
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
7
0
ESCI
RXIE
TXIE
SCIE
ORIE
TEIE
0
0
whenever a message has been successfully trans-
mitted.
Cleared by software to disable transmit interrupt
requests.
Bit 3 = SCIE Status Change Interrupt Enable
−
Set by software to enable an interrupt request
whenever the node’s status changes in run mode or
whenever a dominant pulse is received in standby
mode.
Cleared by software to disable status change inter-
rupt requests.
Bit 2 = ORIE Overrun Interrupt Enable
−
Set by software to enable an interrupt request
whenever a message should be stored and no re-
ceive buffer is avalaible.
Cleared by software to disable overrun interrupt re-
quests.
Bit 1 = TEIE Transmit Error Interrupt Enable
−
Set by software to enable an interrupt whenever an
error has been detected during transmission of a
message.
Cleared by software to disable transmit error inter-
rupts.
Bit 0 = Reserved.
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
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