ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 214
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ST72F521M9T6
Manufacturer Part Number
ST72F521M9T6
Description
IC MCU 8BIT 60K FLASH 80-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F521M9T6.pdf
(215 pages)
Specifications of ST72F521M9T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8244
ST72F521M9T6
ST72F521M9T6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F521M9T6
Manufacturer:
ST
Quantity:
37 800
Company:
Part Number:
ST72F521M9T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST72F521M9T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72F521, ST72521B
16 REVISION HISTORY
Table 34. Revision History
214/215
18-May-2005
7-Dec-2004
4-Mar-2005
Date
Revision
3
4
5
Added
Reinstated
Reinstated “BUSOFF not entered” in
Added “flash only” to PC6 Iinj spec in
Added Note on SMbus to
Static current consumption modified in
Updated footnote and
Modified VtPOR in
Added note 4 below Table of
Corrected MCO description in
Updated footnotes and
Updated soldering information in
Added Suffix 3 to
Updated partnumbers in
Added
Figure 82 on page 153
“Reset pin protection with LVD Enabled” on page 211
“I/O behaviour during ICC mode entry sequence” on page 213
Figure 118 on page 203
section 12.3.2 on page 168
Figure 103
Figure 103
Table 30 on page 205
Section 10.7
“CAN Cell Limitations” on page 212
Table 1
Description of Changes
section 13.3 on page 200
and
and
“CAN Cell Limitations” on page 212
Section 12.2
Figure 104 on page 186
and
section 12.8 on page 182
Figure 104 on page
Section 10.2
and
Section 12.8
186.