ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 130

• Manufacturer Part Number: ST72F521M9T6
• Description: IC MCU 8BIT 60K FLASH 80-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521M9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8244; ST72F521M9T6

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.2 Main Features
– Support of CAN specification 2.0A and 2.0B pas-
– Three prioritized 10-byte Transmit/Receive mes-
– Two programmable global 12-bit message ac-
– Programmable baud rates up to 1 MBit/s
– Buffer flip-flopping capability in transmission
– Maskable interrupts for transmit, receive (one
– Automatic low-power mode after 20 recessive
– Interrupt-driven wake-up from standby mode
– Optional dominant pulse transmission on leaving
– Automatic message queuing for transmission
– Programmable loop-back mode for self-test op-
– Advanced error detection and diagnosis func-
– Software-efficient buffer mapping at a unique ad-
– Scalable architecture.
10.8.3 Functional Description
10.8.3.1 Frame Formats
A summary of all the CAN frame formats is given
in
ard frame format since the extended one is only
acknowledged.
A message begins with a start bit called Start Of
Frame (SOF). This bit is followed by the arbitration
field which contains the 11-bit identifier (ID) and
the Remote Transmission Request bit (RTR). The
RTR bit indicates whether it is a data frame or a re-
mote request frame. A remote request frame does
not have any data byte.
The control field contains the Identifier Extension
bit (IDE), which indicates standard or extended
format, a reserved bit (ro) and, in the last four bits,
a count of the data bytes (DLC). The data field
ranges from zero to eight bytes and is followed by
the Cyclic Redundancy Check (CRC) used as a
frame integrity check for detecting bit errors.
130/215
sive
sage buffers
ceptance filters
per buffer), error and wake-up
bits or on demand (standby mode)
upon reception of dominant pulse
standby mode
upon writing of data byte 7
eration
tions
dress space
Figure 69
for reference. It covers only the stand-
The acknowledgement (ACK) field comprises the
ACK slot and the ACK delimiter. The bit in the ACK
slot is placed on the bus by the transmitter as a re-
cessive bit (logical 1). It is overwritten as a domi-
nant bit (logical 0) by those receivers which have
at this time received the data correctly. In this way,
the transmitting node can be assured that at least
one receiver has correctly received its message.
Note that messages are acknowledged by the re-
ceivers regardless of the outcome of the accept-
ance test.
The end of the message is indicated by the End Of
Frame (EOF). The intermission field defines the
minimum number of bit periods separating con-
secutive messages. If there is no subsequent bus
access by any station, the bus remains idle.
10.8.3.2 Hardware Blocks
The CAN controller contains the following func-
tional blocks (refer to
– ST7 Interface: buffering of the ST7 internal bus
– TX/RX Buffers: three 10-byte buffers for trans-
– ID Filters: two 12-bit compare and don’t care
– PSR: page selection register (see memory map).
– BRPR: clock divider for different data rates.
– BTR: bit timing register.
– ICR: interrupt control register.
– ISR: interrupt status register.
– CSR: general purpose control/status register.
– TECR: transmit error counter register.
– RECR: receive error counter register.
– BTL: bit timing logic providing programmable bit
– BCDL: bit coding logic generating a NRZ-coded
– SHREG: 8-bit shift register for serialization of
– CRC: 15-bit CRC calculator and checker.
– EML: error detection and management logic.
– CAN Core: CAN 2.0B passive protocol control-
and address decoding of the CAN registers.
mission and reception of maximum length mes-
sages.
masks for message acceptance filtering.
sampling and bit clock generation for synchroni-
zation of the controller.
datastream with stuff bits.
data to be transmitted and parallelisation of re-
ceived data.
ler.
Figure
68):