ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 135

• Manufacturer Part Number: ST72F521M9T6
• Description: IC MCU 8BIT 60K FLASH 80-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521M9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8244; ST72F521M9T6

CONTROLLER AREA NETWORK (Cont’d)
10.8.3.4 Bit Timing Logic
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and re-
synchronizing on following edges.
Its operation may be explained simply when the
nominal bit time is divided into three segments as
follows:
– Synchronisation segment (SYNC_SEG): a bit
– Bit segment 1 (BS1): defines the location of the
– Bit segment 2 (BS2): defines the location of the
Figure 72. Bit Timing
change is expected to lie within this time seg-
ment. It has a fixed length of one time quanta (1
x t
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compen-
sate for positive phase drifts due to differences in
the frequency of the various nodes of the net-
work.
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programma-
ble between 1 and 8 time quanta but may also be
automatically shortened to compensate for neg-
ative phase drifts.
CAN
).
SYNC_SEG
1 x t
CAN
BIT SEGMENT 1 (BS1)
t
BS1
NOMINAL BIT TIME
– Resynchronization Jump Width (RJW): de-
To guarantee the correct behaviour of the CAN
controller, SYNC_SEG + BS1 + BS2 must be
greater than or equal to 5 time quanta.
The CAN controller resynchronizes on recessive
to dominant edges only.
For a detailed description of the CAN resynchroni-
zation mechanism and other bit timing configura-
tion constraints, please refer to the Bosch CAN
standard 2.0.
As a safeguard against programming errors, the
configuration of the Bit Timing Register (BTR) is
only possible while the device is in STANDBY
mode.
fines an upper bound to the amount of lengthen-
ing or shortening of the bit segments. It is
programmable between 1 and 4 time quanta.
SAMPLE POINT
BIT SEGMENT 2 (BS2)
t
ST72F521, ST72521B
BS2
TRANSMIT POINT
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