PIC16F76-I/ML Microchip Technology, PIC16F76-I/ML Datasheet - Page 331

• Manufacturer Part Number: PIC16F76-I/ML
• Description: IC MCU FLASH 8KX14 A/D 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F76-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16F76-I/MLR; PIC16F76-I/MLR; PIC16F76I/ML

17.4.18.3 Bus Collision During a STOP Condition
1997 Microchip Technology Inc.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
P
Bus collision occurs during a STOP condition if:
a)
b)
The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is
allow to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded
with SSPADD<6:0> and counts down to 0. After the BRG times out SDA is sampled. If SDA is
sampled low, a bus collision has occurred. This is due to another master attempting to drive a
data '0'
collision occurs. This is another case of another master attempting to drive a data '0'
(Figure
Figure 17-40: Bus Collision During a STOP Condition (Case 1)
Figure 17-41: Bus Collision During a STOP Condition (Case 2)
After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low
after the BRG has timed out.
After the SCL pin is de-asserted, SCL is sampled low before SDA goes high.
(Figure
17-41).
Assert SDA
T
SDA asserted low
BRG
17-40). If the SCL pin is sampled low before SDA is allowed to float high, a bus
T
BRG
Preliminary
T
BRG
T
BRG
Section 17. MSSP
SCL goes low before SDA goes high
Set BCLIF
T
BRG
T
BRG
DS31017A-page 17-55
'0'
'0'
SDA sampled
low after T
Set BCLIF
'0'
'0'
BRG
,
17