PIC16F76-I/ML Microchip Technology, PIC16F76-I/ML Datasheet - Page 236

• Manufacturer Part Number: PIC16F76-I/ML
• Description: IC MCU FLASH 8KX14 A/D 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F76-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16F76-I/MLR; PIC16F76-I/MLR; PIC16F76I/ML

PICmicro MID-RANGE MCU FAMILY
15.4
DS31015A-page 15-16
SSP I
2
C Operation
The SSP module in I
and provides interrupts on start and stop bits in hardware to facilitate software implementations
of the master functions. The SSP module implements the standard mode specifications as well
as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin,
which is the data. The user must configure these pins as inputs through the TRIS bits. The SSP
module functions are enabled by setting SSP Enable bit, SSPEN (SSPCON<5>).
A “glitch” filter is on the SCL and SDA pins when the pin is an input. This filter operates in both
the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there
is a slew rate control of the pin that is independent of device frequency.
Figure 15-7:
SSP Block Diagram (I
2
C mode fully implements all slave functions, except general call support,
SCL
SDA
Appendix A
Read
clock
shift
MSb
2
C Mode)
Stop bit detect
Match detect
SSPADD reg
SSPBUF reg
gives an overview of the I
SSPSR reg
Start and
LSb
Write
(SSPSTAT reg)
data bus
Internal
Set, Reset
S, P bits
Address Match
1997 Microchip Technology Inc.
2
C bus specification.