PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 78

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J90 FAMILY
TABLE 6-3:
DS39933D-page 78
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
LCDPS
LCDSE0
LCDCON
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
Legend:
Note 1:
File Name
(2)
(2)
2:
3:
4:
5:
(2)
(2)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
EUSART Baud Rate Generator Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Control Register 2 (not a physical register)
TRISA7
LATA7
OSCFIP
OSCFIE
INTSRC
OSCFIF
TRISH7
TRISD7
TRISC7
LCDEN
TRISJ7
TRISF7
TRISE7
TRISB7
SPIOD
LATH7
LATD7
LATC7
CSRC
LATJ7
LATF7
LATE7
LATB7
SPEN
U2OD
SE07
Bit 7
WFT
—
—
—
—
—
—
—
PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
(5)
(5)
TRISA6
PLLEN
CCP2OD
BIASMD
LATA6
TRISH6
TRISE6
TRISD6
TRISC6
TRISB6
SLPEN
TRISJ6
TRISF6
LATH6
LATF6
LATE6
LATD6
LATC6
LATB6
LCDIP
LCDIF
LCDIE
LATJ6
U1OD
SE06
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
RX9
TX9
—
(5)
(4)
(5)
CCP1OD
WPROG
TRISH5
TRISF5
TRISE5
TRISD5
TRISC5
TRISB5
TRISA5
TRISJ5
WERR
RC2IP
RC2IE
RC1IP
RC1IE
LATH5
LATF5
LATE5
LATD5
LATC5
LATB5
LATA5
SREN
RC2IF
RC1IF
LATJ5
TXEN
LCDA
TUN5
SE05
Bit 5
—
—
—
—
TRISG4
TRISH4
TRISF4
TRISE4
TRISD4
TRISC4
TRISB4
TRISA4
TRISJ4
LATG4
LATH4
LATF4
LATE4
LATD4
LATC4
LATB4
LATA4
SYNC
CREN
TX2IP
TX2IF
TX2IE
TX1IP
TX1IF
TX1IE
LATJ4
FREE
TUN4
SE04
Bit 4
WA
—
—
—
—
WRERR
CTMUIP
CTMUIF
CTMUIE
TRISH3
TRISG3
TRISD3
TRISC3
SENDB
ADDEN
TRISF3
TRISE3
TRISB3
TRISA3
TRISJ3
LATH3
LATG3
LATD3
LATC3
BCLIP
BCLIE
SSPIP
SSPIF
SSPIE
LATF3
LATE3
LATB3
LATA3
BCLIF
LATJ3
TUN3
SE03
Bit 3
LP3
CS1
CCP2IP
CCP2IF
CCP2IE
TRISH2
TRISG2
TRISD2
TRISC2
TRISJ2
TRISF2
TRISB2
TRISA2
WREN
LATH2
LATG2
LATD2
LATC2
BRGH
LVDIP
LVDIE
LATJ2
LATF2
LATB2
LATA2
FERR
LVDIF
TUN2
SE02
Bit 2
CS0
LP2
—
—
—
—
—
2
C™ Slave mode. See Section 18.4.3.2 “Address
TMR3IP
TMR3IE
TMR2IP
TMR2IE
CCP1IP
CCP1IF
CCP1IE
TMR3IF
TMR2IF
TRISH1
TRISG1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LMUX1
TRISJ1
TRISF1
LATG1
LATH1
LATF1
LATE1
LATD1
LATC1
LATB1
TRMT
OERR
LATJ1
LATA1
TUN1
SE01
Bit 1
LP1
WR
 2010 Microchip Technology Inc.
RTCCIP
RTCCIF
RTCCIE
TMR1IP
TMR1IF
TMR1IE
TRISG0
TRISH0
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LMUX0
TRISJ0
LATG0
LATH0
LATE0
LATD0
LATC0
LATB0
LATA0
LATJ0
TX9D
RX9D
TUN0
SE00
Bit 0
LP0
—
—
—
—
—
—
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
000- 0000
---- ----
--00 x00-
-111 1111
-000 0000
-000 0000
11-- 111-
00-- 000-
00-- 000-
-111 1-11
-000 0-00
-000 0-00
0000 0000
1111 1111
1111 1111
0001 1111
1111 111-
1111 1-11
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
00-x xxxx
xxxx xxx-
xxxx x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
POR, BOR
Value on
Details on
61, 259
61, 267
61, 265
61, 256
61, 257
61, 185
61, 186
61, 184
62, 114
62, 108
62, 113
62, 107
62, 110
62, 112
62, 106
62, 109
62, 138
62, 136
62, 134
62, 132
62, 129
62, 127
62, 125
62, 122
62, 119
62, 138
62, 136
62, 134
62, 132
62, 129
62, 127
62, 125
62, 122
62, 119
62, 111
61, 90
61, 90
37, 62
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