PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 152

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J90 FAMILY
14.1
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
FIGURE 14-1:
FIGURE 14-2:
DS39933D-page 152
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
T13CKI/T1OSO
Timer3 Operation
T1OSI
T1OSI
CCPx Select from T3CON<6,3>
CCPx Select from T3CON<6,3>
Timer1 Oscillator
Timer1 Oscillator
CCPx Special Event Trigger
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
TIMER3 BLOCK DIAGRAM (8-BIT MODE)
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
CCPx Special Event Trigger
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
(1)
(1)
TMR3CS
TMR3CS
Clock
Internal
F
Internal
Clock
F
OSC
OSC
/4
/4
1
0
1
0
Timer1 Clock Input
Timer1 Clock Input
Clear TMR3
Clear TMR3
Prescaler
Prescaler
1, 2, 4, 8
1, 2, 4, 8
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
2
2
with
OSC
TMR3L
TMR3L
/4). When the bit is set, Timer3 increments
8
Timer1,
8
Synchronize
Synchronize
Sleep Input
Sleep Input
Detect
Detect
High Byte
High Byte
TMR3H
TMR3
TMR3
8
 2010 Microchip Technology Inc.
8
the
8
Internal Data Bus
1
0
1
0
Read TMR1L
Write TMR1L
RC1/T1OSI
Set
TMR3IF
on Overflow
Set
TMR3IF
on Overflow
Timer3
On/Off
Timer3
On/Off
and