PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 435

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

INDEX
A
A/D .................................................................................... 289
Absolute Maximum Ratings .............................................. 393
AC (Timing) Characteristics .............................................. 408
ACKSTAT ......................................................................... 245
ACKSTAT Status Flag ...................................................... 245
ADCAL Bit ......................................................................... 297
ADCON0 Register............................................................. 289
ADCON1 Register............................................................. 289
ADCON2 Register............................................................. 289
ADDFSR ........................................................................... 382
ADDLW ............................................................................. 345
Addressable Universal Synchronous Asynchronous
ADDULNK ......................................................................... 382
ADDWF ............................................................................. 345
ADDWFC .......................................................................... 346
ADRESH Register............................................................. 289
ADRESL Register ..................................................... 289, 292
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................. 346
ANDWF ............................................................................. 347
Assembler
AUSART
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A/D Converter Interrupt, Configuring ........................ 293
Acquisition Requirements ......................................... 294
ADCAL Bit................................................................. 297
ADCON0 Register..................................................... 289
ADCON1 Register..................................................... 289
ADCON2 Register..................................................... 289
ADRESH Register............................................. 289, 292
ADRESL Register ..................................................... 289
Analog Port Pins, Configuring................................... 295
Associated Registers ................................................ 297
Automatic Selecting and Configuring
Configuring the Module............................................. 293
Conversion Clock (T
Conversion Requirements ........................................ 426
Conversion Status (GO/DONE Bit) ........................... 292
Conversions .............................................................. 296
Converter Calibration ................................................ 297
Converter Characteristics ......................................... 425
Operation in Power-Managed Modes ....................... 297
Special Event Trigger (CCP)..................................... 296
Use of the CCP2 Trigger........................................... 296
Load Conditions for Device
Parameter Symbology .............................................. 408
Temperature and Voltage Specifications .................. 409
Timing Conditions ..................................................... 409
GO/DONE Bit............................................................ 292
Receiver Transmitter (AUSART). See AUSART.
MPASM Assembler................................................... 390
Asynchronous Mode ................................................. 280
Baud Rate Generator (BRG)..................................... 278
Acquisition Time ............................................... 295
Associated Registers, Receive ......................... 283
Associated Registers, Transmit ........................ 281
Receiver............................................................ 282
Setting up 9-Bit Mode with
Transmitter........................................................ 280
Associated Registers ........................................ 278
Baud Rate Error, Calculating ............................ 278
Timing Specifications ....................................... 409
Address Detect ......................................... 282
AD
) ............................................ 295
PIC18F87J90 FAMILY
B
Baud Rate Generator ....................................................... 241
BC..................................................................................... 347
BCF .................................................................................. 348
BF ..................................................................................... 245
BF Status Flag .................................................................. 245
Bias Generation (LCD)
Block Diagrams
Synchronous Master Mode....................................... 284
Synchronous Slave Mode......................................... 287
Charge Pump Design Considerations ...................... 193
A/D............................................................................ 292
Analog Input Model................................................... 293
AUSART Receive ..................................................... 282
AUSART Transmit .................................................... 280
Baud Rate Generator ............................................... 241
Capture Mode Operation .......................................... 176
Clock Source Multiplexing ........................................ 166
Comparator Analog Input Model............................... 303
Comparator I/O Operating Modes ............................ 300
Comparator Output................................................... 302
Comparator Voltage Reference................................ 306
Comparator Voltage Reference
Compare Mode Operation ........................................ 177
Connections for On-Chip Voltage Regulator ............ 333
CTMU ....................................................................... 309
CTMU Current Source Calibration Circuit ................ 312
CTMU Typical Connections and Internal
CTMU Typical Connections and Internal
Device Clock............................................................... 35
EUSART Receive ..................................................... 266
EUSART Transmit .................................................... 264
External Power-on Reset Circuit
Fail-Safe Clock Monitor ............................................ 335
Generic I/O Port Operation....................................... 117
Interrupt Logic........................................................... 102
LCD Clock Generation.............................................. 188
LCD Driver Module ................................................... 183
LCD Regulator Connections (M0 and M1) ............... 190
MSSP (I
MSSP (I
MSSP (SPI Mode) .................................................... 211
On-Chip Reset Circuit................................................. 53
PIC18F6XJ90 (64-Pin) ............................................... 12
PIC18F8XJ90 (80-Pin) ............................................... 13
PLL ............................................................................. 40
PWM Operation (Simplified) ..................................... 179
Baud Rates, Asynchronous Modes .................. 279
High Baud Rate Select (BRGH Bit) .................. 278
Operation in Power-Managed Modes............... 278
Sampling .......................................................... 278
Associated Registers, Receive......................... 286
Associated Registers, Transmit........................ 285
Reception ......................................................... 286
Transmission .................................................... 284
Associated Registers, Receive......................... 288
Associated Registers, Transmit........................ 287
Reception ......................................................... 288
Transmission .................................................... 287
Output Buffer Example ..................................... 307
Configuration for Pulse Delay Generation ........ 320
Configuration for Time Measurement ............... 319
(Slow V
2
2
C Master Mode)......................................... 239
C Mode)..................................................... 220
DD
Power-up) ......................................... 55
DS39933D-page 435