PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 332

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J90 FAMILY
REGISTER 25-9:
TABLE 25-3:
DS39933D-page 332
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
REGSLP
Name
R/W-0
2:
(1)
The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
REGSLP
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator continues to operate normally in Sleep mode
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
U-0
—
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit 6
—
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Bit 5
CM
—
U-0
Bit 4
—
RI
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
TO
—
U-0
—
Bit 2
PD
—
(2)
(1)
U-0
—
Bit 1
POR
—
 2010 Microchip Technology Inc.
x = Bit is unknown
SWDTEN
U-0
Bit 0
BOR
—
Reset Values
SWDTEN
on page
R/W-0
60
60
bit 0
(2)