PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 77

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 6-3:
 2010 Microchip Technology Inc.
TMR0H
TMR0L
T0CON
OSCCON
LCDREG
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
LCDDATA4
LCDDATA3
LCDDATA2
LCDDATA1
LCDDATA0
LCDSE5
LCDSE4
LCDSE3
LCDSE2
LCDSE1
CVRCON
CMCON
TMR3H
TMR3L
T3CON
Legend:
Note 1:
File Name
2:
3:
4:
5:
(2)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
TMR0ON
TRIGSEL
REGSLP
S39C0
CVREN
ADCAL
SE39
C2OUT
WCOL
S31C0
S23C0
S15C0
S07C0
IDLEN
GCEN
GCEN
ADFM
RD16
SE47
SE31
SE23
SE15
RD16
IPEN
Bit 7
SMP
—
—
PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
(2)
(2)
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ACKSTAT
ACKSTAT
S38C0
T3CCP2
SSPOV
SE38
CVROE
T08BIT
T1RUN
C1OUT
IRCF2
S30C0
S22C0
S14C0
S06C0
CPEN
SE46
SE30
SE22
SE14
Bit 6
CKE
—
—
—
—
—
(2)
(2)
2
ADMSK5
C™ Slave mode. MSSP1 Baud Rate Reload Register in I
T1CKPS1
T3CKPS1
S37C0
SSPEN
ACKDT
VCFG1
ACQT2
S29C0
S21C0
S13C0
S05C0
IRCF1
C2INV
BIAS2
S37
CVRR
T0CS
CHS3
SE45
SE29
SE21
SE13
Bit 5
D/A
CM
—
(2)
(2)
(3)
ADMSK4
T1CKPS0
T3CKPS0
S36C0
ACKEN
SE36
CVRSS
VCFG0
ACQT1
S28C0
S20C0
S12C0
S04C0
IRCF0
BIAS1
C1INV
CHS2
T0SE
SE44
SE28
SE20
SE12
Bit 4
CKP
—
RI
P
(2)
(2)
(3)
ADMSK3
T1OSCEN
S35C0
T3CCP1
SSPM3
PCFG3
ACQT0
SE35
S27C0
S19C0
S11C0
S03C0
BIAS0
RCEN
OSTS
CHS1
CVR3
SE43
SE27
SE19
SE11
Bit 3
PSA
CIS
TO
—
S
PIC18F87J90 FAMILY
(2)
(2)
(3)
ADMSK2
TMR2ON
MODE13
S34C0
T1SYNC
T3SYNC
SSPM2
PCFG2
ADCS2
SE34
T0PS2
S26C0
S18C0
S10C0
S02C0
CHS0
CVR2
SE42
SE26
SE18
SE10
IOFS
Bit 2
PEN
CM2
R/W
PD
—
(2)
(2)
(3)
2
C™ Slave mode. See Section 18.4.3.2 “Address
ADMSK1
GO/DONE
T2CKPS1
TMR1CS
TMR3CS
S33C0
CKSEL1
SE33
SSPM1
PCFG1
ADCS1
T0PS1
2
S25C0
S17C0
S09C0
S01C0
RSEN
SCS1
CVR1
SE41
SE25
SE17
SE09
Bit 1
POR
C Master mode.
CM1
UA
—
(2)
(2)
(3)
T2CKPS0
SWDTEN
TMR1ON
TMR3ON
CKSEL0
SSPM0
PCFG0
ADCS0
T0PS0
S32C0
S24C0
S16C0
S08C0
S00C0
ADON
SCS0
CVR0
SE40
SE32
SE24
SE16
SE08
Bit 0
BOR
SEN
SEN
CM0
BF
0000 0000
xxxx xxxx
1111 1111
0110 q000
-011 1100
0--- ---0
0-11 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
0-00 0000
0-00 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
DS39933D-page 77
Value on
Details on
60, 219,
60, 212,
60, 213,
60, 223,
60, 141
60, 141
60, 141
60, 189
60, 332
60, 147
60, 147
60, 143
60, 150
60, 150
60, 149
60, 254
61, 297
61, 297
61, 289
61, 290
61, 291
61, 187
61, 187
61, 187
61, 187
61, 187
61, 187
61, 187
61, 187
61, 187
61, 187
61, 305
61, 299
61, 153
61, 153
61, 151
36, 60
54, 60
page
254
221
222
224