PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 219

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.9
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTRC source. See Section 3.3 “Clock Sources
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
TABLE 18-2:
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISF
TRISG
SSPBUF
SSPCON1
SSPSTAT
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Name
OPERATION IN POWER-MANAGED
MODES
MSSP Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
TRISC7
TRISF7
SPIOD
WCOL
Bit 7
SMP
—
—
—
REGISTERS ASSOCIATED WITH SPI OPERATION
CCP2OD
TRISC6
TRISF6
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
CCP1OD
TRISC5
TRISF5
SSPEN
RC1IE
RC1IP
RC1IF
Bit 5
D/A
TRISC4
TRISG4
TRISF4
INT0IE
TX1IE
TX1IP
TX1IF
Bit 4
CKP
P
PIC18F87J90 FAMILY
TRISG3
TRISC3
TRISF3
SSPM3
SSPIE
SSPIP
SSPIF
mode and
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
18.3.10
A Reset disables the MSSP module and terminates the
current transfer.
18.3.11
Table 18-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 18-1:
There is also an SMP bit which controls when the data
is sampled.
RBIE
Bit 3
S
Standard SPI Mode
Terminology
0, 0
0, 1
1, 0
1, 1
TMR0IF
TRISC2
TRISG2
TRISF2
SSPM2
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
Bit 2
R/W
—
—
—
data
SPI BUS MODES
to be
TMR2IF
TMR2IE
TMR2IP
TRISG1
TRISC1
TRISF1
SSPM1
INT0IF
Bit 1
UA
shifted into
Control Bits State
CKP
0
0
1
1
TMR1IF
TMR1IE
TMR1IP
TRISC0
TRISG0
SSPM0
RBIF
Bit 0
DS39933D-page 219
BF
—
CKE
on page
the SPI
Values
Reset
1
0
1
0
59
62
62
62
62
62
62
60
60
60