PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 75

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.4
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F60h to FFFh). A list
of these registers is given in Table 6-2 and Table 6-3.
TABLE 6-2:
 2010 Microchip Technology Inc.
Note 1:
FEDh POSTDEC0
FECh PREINC0
Addr.
FFDh
FFCh
FEEh POSTINC0
FEBh PLUSW0
FEAh
FFEh
FFBh
FEFh
FFFh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h PREINC1
FE3h PLUSW1
FE2h
FE1h
FE0h
2:
3:
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
Name
TOSU
TOSH
TOSL
PCL
BSR
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on PIC18F6XJ90 devices.
SPECIAL FUNCTION REGISTERS
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J90 FAMILY DEVICES
FDDh POSTDEC2
FDCh PREINC2
FCDh
FCCh
Addr.
FDEh POSTINC2
FDBh PLUSW2
FDAh
FCEh
FCBh
FCAh
FDFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FC9h
FC8h
FC7h
FC6h SSPCON1
FC5h SSPCON2
FC4h
FC3h
FC2h
FC1h
FC0h
WDTCON
SSPSTAT
OSCCON
LCDREG
ADRESH
ADCON0
ADCON1
ADCON2
SSPBUF
SSPADD
ADRESL
INDF2
STATUS
TMR0H
T0CON
TMR1H
T1CON
T2CON
FSR2H
TMR0L
TMR1L
FSR2L
RCON
Name
TMR2
—
PR2
(2)
(1)
(1)
(1)
(1)
(1)
Addr.
FBDh LCDDATA2
FBCh LCDDATA1
FBFh LCDDATA4
FBEh LCDDATA3
FBBh LCDDATA0
FBAh LCDSE5
FAEh
FADh
FACh
FABh
FAAh
FB9h LCDSE4
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CVRCON
RCREG1
LCDCON
SPBRG1
EECON2
EECON1
LCDSE3
LCDSE2
LCDSE1
TXREG1
RCSTA1
LCDSE0
CMCON
TXSTA1
TMR3H
TMR3L
T3CON
LCDPS
Name
IPR3
PIR3
IPR2
PIR2
PIE3
PIE2
—
(2)
(3)
(3)
(3)
Addr.
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh OSCTUNE F7Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F99h TRISH
F97h
F96h
F94h
F93h
F92h
F91h
F90h
F8Fh
F89h
F88h PORTJ
F87h PORTH
F86h
F85h
F84h
F83h
F82h
F81h
F80h
F98h
F95h
PIC18F87J90 FAMILY
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TRISJ
LATH
PORTG
PORTE
PORTD
PORTC
PORTB
PORTF
PORTA
LATJ
TRISG
TRISD
TRISC
TRISF
TRISE
TRISB
TRISA
Name
LATG
LATF
LATE
LATD
LATC
LATB
LATA
IPR1
PIR1
PIE1
—
(2)
(3)
(3)
(3)
(3)
(3)
(3)
Addr.
F7Dh LCDDATA23
F7Ch LCDDATA22
F6Dh
F6Ch
F7Eh BAUDCON1
F7Ah
F6Eh
F6Bh LCDDATA5
F6Ah
F7Fh
F6Fh
F79h
F78h
F77h LCDDATA17
F76h LCDDATA16
F75h
F74h
F73h
F72h
F71h LCDDATA11
F70h LCDDATA10
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
LCDDATA21
LCDDATA20
LCDDATA19
LCDDATA18
LCDDATA15
LCDDATA14
LCDDATA13
LCDDATA12
LCDDATA9
LCDDATA8
LCDDATA7
LCDDATA6
CCP1CON
CCP2CON
SPBRGH1
CCPR1H
CCPR2H
RCREG2
SPBRG2
TXREG2
CCPR1L
CCPR2L
RCSTA2
TXSTA2
Name
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Addr.
F5Eh
F5Dh
F5Ch
F5Bh
F5Ah
F5Fh
F59h
F58h
F57h CTMUCONH
F56h CTMUCONL
F55h
F54h
DS39933D-page 75
CTMUICON
ALRMVALH
ALRMVALL
ALRMCFG
ALRMRPT
PADCFG1
RTCVALH
RTCVALL
RTCCFG
RTCCAL
Name