PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 71
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PIC18F86J90-I/PT
Manufacturer Part Number
PIC18F86J90-I/PT
Description
IC PIC MCU FLASH 64KB 80-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F67J90-IPT.pdf
(450 pages)
2.PIC18F67J90-IPT.pdf
(3 pages)
3.PIC18F67J90-IPT.pdf
(10 pages)
4.PIC18F66J90-IPT.pdf
(444 pages)
Specifications of PIC18F86J90-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
67
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3923 B
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
67
Number Of Timers
4
Operating Supply Voltage
2.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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6.2.3
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte (LSB) of an
instruction word is always stored in a program memory
location with an even address (LSB = 0). To maintain
alignment
increments in steps of 2 and the LSB will always read
‘0’ (see Section 6.1.3 “Program Counter”).
Figure 6-5 shows an example of how instruction words
are stored in the program memory.
FIGURE 6-5:
6.2.4
The standard PIC18 instruction set has four, two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits (MSb); the other
12 bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
EXAMPLE 6-4:
2010 Microchip Technology Inc.
CASE 1:
Object Code
CASE 2:
Object Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
INSTRUCTIONS IN PROGRAM
MEMORY
TWO-WORD INSTRUCTIONS
with
Instruction 1:
Instruction 2:
Instruction 3:
instruction
INSTRUCTIONS IN PROGRAM MEMORY
TWO-WORD INSTRUCTIONS
Program Memory
Byte Locations
MOVLW
GOTO
MOVFF
Source Code
TSTFSZ
Source Code
MOVFF
ADDWF
TSTFSZ
MOVFF
ADDWF
boundaries,
055h
0006h
123h, 456h
REG1
REG1, REG2 ; No, skip this word
REG3
REG1
REG1, REG2 ; Yes, execute this word
REG3
the
PC
LSB = 1
; is RAM location 0?
; Execute this word as a NOP
; continue code
; is RAM location 0?
; 2nd word of instruction
; continue code
EFh
C1h
0Fh
F0h
F4h
PIC18F87J90 FAMILY
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in Figure 6-5 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.
Note:
LSB = 0
55h
03h
00h
23h
56h
See Section 6.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
Word Address
00000Ah
00000Ch
00000Eh
000000h
000002h
000004h
000006h
000008h
000010h
000012h
000014h
DS39933D-page 71
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