PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 97

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.2
Master mode operation is supported in firmware using
interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a RESET, or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I
bus is IDLE and both the S and P bits are clear.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB<4,1> bit(s). The output level is always low, irre-
spective of the value(s) in PORTB<4,1>. So, when
transmitting data, a ‘1’ data bit must have the
TRISB<1> bit set (input) and a ‘0’ data bit must have
the TRISB<1> bit cleared (output). The same scenario
is true for the SCL line with the TRISB<4> bit. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode operation can be done with either the
Slave mode IDLE (SSPM3:SSPM0 = 1011) or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Master mode operation, see
Application Note AN554, “Software Implementation of
I
TABLE 10-3:
 2003 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
13h
93h
14h
94h
86h
Legend:
Note 1:
2
C™ Bus Master”.
Address
2
C bus may be taken when the P bit is set, or the
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI mode.
Maintain these bits clear in I
MASTER MODE OPERATION
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISB
Name
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port (I
PORTB Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
SMP
WCOL
Bit 7
GIE
—
—
(1)
SSPOV
CKE
PEIE
ADIF
ADIE
Bit 6
2
(1)
C mode.
2
C module.
TMR0IE
SSPEN
RCIE
RCIF
Bit 5
D/A
2
C mode) Address Register
Preliminary
Bit 4
INTE
TXIF
TXIE
CKP
P
2
SSPM3 SSPM2 SSPM1 SSPM0
C OPERATION
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
RBIE
Bit 3
S
10.3.3
In Multi-Master mode operation, the interrupt genera-
tion on the detection of the START and STOP condi-
tions allows the determination of when the bus is free.
The STOP (P) and START (S) bits are cleared from a
RESET, or when the SSP module is disabled. The
STOP (P) and START (S) bits will toggle based on the
START and STOP conditions. Control of the I
may be taken when bit P (SSPSTAT<4>) is set, or the
bus is IDLE and both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the STOP condition occurs.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected out-
put level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISB<4,1>). There are two stages
where this arbitration can be lost:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave device con-
tinues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data trans-
fer stage, the device will need to re-transfer the data at
a later time.
For more information on Multi-Master mode operation,
see Application Note AN578, “Use of the SSP Module
in the of I
TMR0IF
Bit 2
R/W
2
C™ Multi-Master Environment”.
MULTI-MASTER MODE OPERATION
Bit 1
INTF
UA
PIC16F87/88
RBIF
Bit 0
BF
0000 000x 0000 000u
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
POR, BOR
Value on
DS30487B-page 95
Value on
RESETS
all other
2
C bus