PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 208

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

P
T
T1CKPS0 Bit ...................................................................... 72
T1CKPS1 Bit ...................................................................... 72
T1CON Register ................................................................. 14
T1OSCEN Bit ..................................................................... 72
T1SYNC Bit ........................................................................ 72
T2CKPS0 Bit ...................................................................... 80
T2CKPS1 Bit ...................................................................... 80
T2CON Register ................................................................. 14
T
Time-out Sequence .......................................................... 134
Timer0 ................................................................................ 67
Timer1 ................................................................................ 71
Timer2 ................................................................................ 79
Timing Diagrams
DS30487B-page 206
AD
I C
................................................................................... 118
Associated Registers ................................................. 69
Clock Source Edge Select (T0SE Bit) ........................ 18
Clock Source Select (T0CS Bit) ................................. 18
External Clock ............................................................ 68
Interrupt ...................................................................... 67
Operation ................................................................... 67
Overflow Enable (TMR0IE Bit) ................................... 19
Overflow Flag (TMR0IF Bit) ..................................... 140
Overflow Interrupt ..................................................... 140
Prescaler .................................................................... 68
T0CKI ......................................................................... 68
Associated Registers ................................................. 77
Asynchronous Counter Mode ..................................... 74
Capacitor Selection .................................................... 75
Counter Operation ...................................................... 73
Operation ................................................................... 71
Operation in Timer Mode ........................................... 73
Oscillator .................................................................... 75
Oscillator Layout Considerations ............................... 75
Prescaler .................................................................... 76
Resetting Timer1 Register Pair .................................. 76
Resetting Timer1 Using a CCP Trigger Output .......... 75
Synchronized Counter Mode ...................................... 73
Use as a Real-Time Clock ......................................... 76
Associated Registers ................................................. 80
Output ........................................................................ 79
Postscaler .................................................................. 79
Prescaler .................................................................... 79
Prescaler and Postscaler ........................................... 79
A/D Conversion ........................................................ 189
Asynchronous Master Transmission ........................ 103
Asynchronous Master Transmission
Asynchronous Reception ......................................... 104
Asynchronous Reception with
Asynchronous Reception with Address Detect ........ 107
Brown-out Reset ...................................................... 179
Capture/Compare/PWM (CCP1) .............................. 181
CLKO and I/O ........................................................... 178
External Clock .......................................................... 177
Fail-Safe Clock Monitor ............................................ 144
I
I
I
I
Primary System Clock after RESET
2
2
2
2
C Bus Data ............................................................ 185
C Bus START/STOP Bits ...................................... 184
C Reception (7-bit Address) .................................... 94
C Transmission (7-bit Address) ............................... 94
Reading and Writing .......................................... 74
(Back to Back) .................................................. 103
Address Byte First ............................................ 107
(EC, RC, INTRC) ............................................... 48
1 6 F
8 7 / 8 8
Timing Parameter Symbology .......................................... 176
Timing Requirements
TMR0 Register ................................................................... 14
TMR1CS Bit ....................................................................... 72
TMR1H Register ................................................................ 14
TMR1L Register ................................................................. 14
TMR1ON Bit ....................................................................... 72
TMR2 Register ................................................................... 14
TMR2ON Bit ....................................................................... 80
TMRO Register .................................................................. 16
TOUTPS0 Bit ..................................................................... 80
TOUTPS1 Bit ..................................................................... 80
TOUTPS2 Bit ..................................................................... 80
TOUTPS3 Bit ..................................................................... 80
TRISA Register .............................................................15, 51
TRISB Register .................................................................. 15
Two-Speed Clock Start-up Mode ..................................... 143
Two-Speed Start-up ......................................................... 129
TXREG Register ................................................................ 14
Primary System Clock after RESET (HS, XT, LP) ..... 47
PWM Output .............................................................. 84
RESET, Watchdog Timer, Oscillator Start-up
Slow Rise Time (MCLR Tied to V
SPI Master Mode ....................................................... 91
SPI Master Mode (CKE = 0, SMP = 0) .................... 182
SPI Master Mode (CKE = 1, SMP = 1) .................... 182
SPI Slave Mode (CKE = 0) .................................91, 183
SPI Slave Mode (CKE = 1) .................................91, 183
Switching to SEC_RUN Mode ................................... 44
Synchronous Reception (Master Mode, SREN) ...... 111
Synchronous Transmission ..................................... 109
Synchronous Transmission (Through TXEN) .......... 109
Time-out Sequence on Power-up (MCLR Tied
Time-out Sequence on Power-up (MCLR Tied
Time-out Sequence on Power-up (MCLR Tied
Timer0 and Timer1 External Clock .......................... 180
Timer1 Incrementing Edge ........................................ 73
Transition Between SEC_RUN/RC_RUN
Two-Speed Start-up Mode ....................................... 143
USART Synchronous Receive (Master/Slave) ........ 187
USART Synchronous Transmission
Wake-up from SLEEP via Interrupt .......................... 146
XT, HS, LP, EC and EXTRC to RC_RUN Mode ........ 43
A/D Conversion ........................................................ 189
Capture/Compare/PWM (CCP1) ............................. 181
CLKO and I/O .......................................................... 178
External Clock .......................................................... 177
I
I
RESET, Watchdog Timer, Oscillator
SPI Mode ................................................................. 184
Timer0 and Timer1 External Clock .......................... 180
USART Synchronous Receive ................................. 187
USART Synchronous Transmission ........................ 187
2
2
C Bus Data ............................................................ 186
C Bus START/STOP Bits ...................................... 185
Timer and Power-up Timer .............................. 179
Through RC Network) ...................................... 138
to V
to V
to V
and Primary Clock ............................................. 46
(Master/Slave) ................................................. 187
Start-up Timer, Power-up Timer and
Brown-out Reset .............................................. 179
DD
DD
DD
Through Pull-up Resistor) .................... 137
Through RC Network): Case 1 ............. 137
Through RC Network): Case 2 ............. 137
 2003 Microchip Technology Inc.
DD