PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 47

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.7.3
When switching from a SEC_RUN or RC_RUN mode
back to the primary system clock, following a change
of SCS<1:0> to ‘00’, the sequence of events that take
place will depend upon the value of the F
the Configuration register. If the primary clock source
is configured as a crystal (HS, XT, or LP), then the
transition will take place after 1024 clock cycles. This
is necessary because the crystal oscillator had been
powered down until the time of the transition. In order
to provide the system with a reliable clock when the
changeover has occurred, the clock will not be
released to the changeover circuit until the 1024 count
has expired.
During the oscillator start-up time, the system clock
comes from the current system clock. Instruction exe-
cution and/or peripheral operation continues using the
currently selected oscillator as the CPU clock source,
until the necessary clock count has expired to ensure
that the primary system clock is stable.
To know when the OST has expired, the OSTS bit
should be monitored. OSTS = 1 indicates that the
Oscillator Start-up Timer has timed out and the system
clock comes from the primary clock source.
Following the oscillator start-up time, the internal Q
clocks are held in the Q1 state until eight falling edge
clocks are counted from the primary system clock. The
clock input to the Q clocks is then released, and oper-
ation resumes with primary system clock determined
by the F
When in SEC_RUN mode, the act of clearing the
T1OSCEN bit in the T1CON register will cause
SCS<0> to be cleared, which causes the SCS<1:0>
bits to revert to ‘00’ or ‘10’, depending on what SCS<1>
is. Although the T1OSCEN bit was cleared, T1OSC will
be enabled and instruction execution will continue until
the OST time-out for the main system clock is com-
plete. At that time, the system clock will switch from the
T1OSC to the primary clock or the INTRC. Following
this, the T1 oscillator will be shut down.
 2003 Microchip Technology Inc.
Note:
OSC
SEC_RUN/RC_RUN TO PRIMARY
CLOCK SOURCE
If the primary system clock is either RC or
EC, an internal delay timer (5-10 s) will
suspend operation after exiting Secondary
Clock mode to allow the CPU to become
ready for code execution.
bits (see Figure 4-10).
OSC
bits in
Preliminary
4.7.3.1
Changing back to the primary oscillator from
SEC_RUN or RC_RUN can be accomplished by either
changing SCS<1:0> to ‘00’, or clearing the T1OSCEN
bit in the T1CON register (if T1OSC was the secondary
clock).
The sequence of events that follows is the same for
both modes:
1.
2.
3.
4.
5.
6.
7.
If the primary system clock is configured as EC,
RC, or INTRC, then the OST time-out is
skipped. Skip to step 3.
If the primary system clock is configured as an
external oscillator (HS, XT, LP), then the OST
will be active, waiting for 1024 clocks of the
primary system clock.
On the following Q1, the device holds the
system clock in Q1.
The device stays in Q1 while eight falling edges
of the primary system clock are counted.
Once the eight counts transpire, the device
begins to run from the primary oscillator.
If the secondary clock was INTRC and the pri-
mary is not INTRC, the INTRC will be shut down
to save current, providing that the INTRC is not
being used for any other function, such as WDT,
or Fail-Safe Clock monitoring.
If the secondary clock was T1OSC, the T1OSC
will continue to run if T1OSCEN is still set,
otherwise the T1 oscillator will be shut down.
Returning to Primary Clock Source
Sequence
PIC16F87/88
DS30487B-page 45