PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 94

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87/88
10.3
The SSP module in I
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementations of the master func-
tions. The SSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RB4/SCK/SCL pin, which is the clock (SCL), and the
RB1/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISB<4,1> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 10-5:
The SSP module has five registers for I
• SSP Control register (SSPCON)
• SSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer register (SSPBUF)
• SSP Shift register (SSPSR) - Not directly
• SSP Address register (SSPADD)
DS30487B-page 92
RB4/SCK/
SCL
RB1/
accessible
SDA
SDI/
SSP I
Read
Clock
Shift
2
C Mode Operation
MSb
2
C mode fully implements all slave
STOP Bit Detect
SSP BLOCK DIAGRAM
(I
SSPADD Reg
SSPBUF Reg
Match Detect
SSPSR Reg
START and
2
C MODE)
LSb
Write
Set, RESET
S, P Bits
(SSPSTAT Reg)
2
Addr Match
C operation:
Internal
Data Bus
Preliminary
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISB bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I
Additional information on SSP I
found in the PICmicro
Manual (DS33023).
10.3.1
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISB<4,1> set). The SSP module will
override the input state with the output data, when
required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
Either or both of the following conditions will cause the
SSP module not to give this ACK pulse:
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit, BF, is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
module, are shown in timing parameter #100 and
parameter #101.
2
C specification, as well as the requirement of the SSP
STOP bit interrupts enabled to support firmware
Master mode
STOP bit interrupts enabled to support Firmware
Master mode
START and STOP bit interrupts enabled, Slave is
IDLE
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with START and
C Slave mode (10-bit address), with START and
C firmware controlled master operation with
The buffer full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
The overflow bit, SSPOV (SSPCON<6>), was
set before the transfer was received.
SLAVE MODE
2
C module.
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
®
 2003 Microchip Technology Inc.
Mid-Range MCU Reference
2
C operation may be
2
C opera-