PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 43

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 4-6:
4.6.4
The IRCF bits can be modified at any time, regardless
of which clock source is currently being used as the sys-
tem clock. The internal oscillator allows users to change
the frequency during run time. This is achieved by mod-
ifying the IRCF bits in the OSCCON register. The
sequence of events that occur after the IRCF bits are
modified is dependent upon the initial value of the IRCF
bits before they are modified. If the INTRC (31.25 kHz,
IRCF<2:0> = 000) is running and the IRCF bits are
modified to any other value than ‘000’, a 4 ms clock
switch delay is turned on. Code execution continues at
a higher than expected frequency while the new fre-
quency stabilizes. Time sensitive code should wait for
the IOFS bit in the OSCCON register to become set
before continuing. This bit can be monitored to ensure
that the frequency is stable before using the system
clock in time critical applications.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz IRCF<2:0>
4 ms clock switch delay. The new INTOSC frequency
will be stable immediately after the eight falling edges.
The IOFS bit will remain set after clock switching
occurs.
 2003 Microchip Technology Inc.
Note:
T1OSO
T1OSI
OSC2
OSC1
MODIFYING THE IRCF BITS
Caution must be taken when modifying the
IRCF bits using BCF or BSF instructions. It
is possible to modify the IRCF bits to a fre-
quency that may be out of the V
cation range; for example, V
IRCF = 111 (8 MHz).
Primary Oscillator
Secondary Oscillator
31.25 kHz
PIC16F87/88 CLOCK DIAGRAM
(INTRC)
000), there is no need for a
Oscillator
31.25 kHz
Internal
Source
SLEEP
T1OSCEN
Enable
Oscillator
Block
(INTOSC)
8 MHz
DD
= 2.0V and
DD
specifi-
Preliminary
31.25 kHz
500 kHz
250 kHz
125 kHz
8 MHz
4 MHz
2 MHz
1 MHz
OSCCON<6:4>
4.6.5
Following are three different sequences for switching
the internal RC oscillator frequency.
• Clock before switch: 31.25 kHz (IRCF<2:0> = 000)
1.
2.
3.
4.
5.
• Clock before switch: One of INTOSC/INTOSC
1.
2.
3.
4.
111
110
101
100
011
010
001
000
postscaler (IRCF<2:0>
To Timer1
IRCF bits are modified to an INTOSC/INTOSC
postscaler frequency.
The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
The IOFS bit is clear to indicate that the clock is
unstable and a 4 ms delay is started. Time
dependent code should wait for IOFS to become
set.
Switchover is complete.
IRCF
(IRCF<2:0> = 000).
The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
Oscillator switchover is complete.
LP, XT, HS, RC, EC
CLOCK TRANSITION SEQUENCE
bits
Internal Oscillator
are
T1OSC
PIC16F87/88
Config1(F
SCS<1:0>(T1OSC)
modified
000)
OSC
2:F
OSC
DS30487B-page 41
0)
WDT, FSCM
to
Peripherals
INTRC
CPU