PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 34

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87/88
3.7
FLASH program memory may only be written to if the
destination address is in a segment of memory that is
not write protected, as defined in bits WRT1:WRT0 of
the device configuration word (Register 15-1). FLASH
program memory must be written in four-word blocks.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where EEADR<1:0> = 00. At the same time,
all block writes to program memory are done as write
only operations. The program memory must first be
erased. The write operation is edge-aligned, and
cannot occur across boundaries.
To write to the program memory, the data must first be
loaded into the buffer registers. There are four 14-bit
buffer registers and they are addressed by the low
2 bits of EEADR.
Loading data into the buffer registers is accomplished
via the EEADR, EEADT, EECON1 and EECON2
registers as follows:
• Set EECON1 PGD and WREN
• Write address to EEADRH:EEADR
• Write data to EEDATA:EEDATH
• Write 55, AA to EECON2
• Set WR bit in EECON1
FIGURE 3-1:
DS30487B-page 32
EEADR<1:0>
First word of block
to be written
Writing to FLASH Program
Memory
=
00
Buffer Register
14
BLOCK WRITES TO FLASH PROGRAM MEMORY
EEADR<1:0>
7
= 01
Buffer Register
5
EEDATH
14
6
Program Memory
Preliminary
EEADR<1:0>
0 7
There are 4 buffer register words and all four locations
MUST be written to with correct data.
After
EEADR
This short write only transfers the data to the buffer reg-
ister. The WR bit will be cleared in hardware after 1
cycle. The core will not halt and there will be no
EEWHLT signal generated.
After
EEADR = xxxxxx11, then a long write will occur. This
will
EEDATH:EEDATA to the buffer registers and begin the
write of all four words. The processor will execute the
next instruction and then ignore the subsequent
instruction. The user should place NOP instructions into
the second words. The processor will then halt internal
operations for typically 2 msec in which the write takes
place. This is not SLEEP mode, as the clocks and
peripherals will continue to run. After the write cycle,
the processor will resume operation with the 3rd
instruction after the EECON1 write instruction.
After each long write, the 4 buffer registers will be reset
to 3FFF.
= 10
EEDATA
Buffer Register
simultaneously
the
the
xxxxxx11, then a short write will occur.
8
14
“BSF
“BSF
0
EEADR<1:0>
EECON1,WR”
EECON1,WR”
 2003 Microchip Technology Inc.
transfer
= 11
Buffer Register
All buffers are
to FLASH
automatically
after this word
is written
transferred
the
14
instruction,
instruction,
data
from
if
if