PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 32

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87/88
3.5
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit
(EECON1<7>),
(EECON1<0>). Once the read control bit is set, the
program memory FLASH controller will use the second
instruction cycle to read the data. This causes the
second instruction immediately following the “BSF
EECON1,RD” instruction to be ignored. The data is
available in the very next cycle in the EEDATA and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATA and
EEDATH registers will hold this value until another read
or until it is written to by the user (during a write
operation).
EXAMPLE 3-3:
DS30487B-page 30
BANKSEL EEADRH
MOVF
MOVWF
MOVF
MOVWF
BANKSEL EECON1
BSF
BSF
NOP
NOP
BANKSEL EEDATA
MOVF
MOVWF
MOVF
MOVWF
Reading FLASH Program Memory
ADDRH, W
EEADRH
ADDRL, W
EEADR
EECON1, EEPGD ; Point to PROGRAM
EECON1, RD
EEDATA, W
DATAL
EEDATH, W
DATAH
and
FLASH PROGRAM READ
then
; Select Bank of EEADRH
;
; MS Byte of Program
; Address to read
;
; LS Byte of Program
; Address to read
; Select Bank of EECON1
; memory
; EE Read
;
; Any instructions
; here are ignored as
; program memory is
; read in second cycle
; after BSF EECON1,RD
; Select Bank of EEDATA
; DATAL = EEDATA
;
; DATAH = EEDATH
;
set
control
bit
Preliminary
RD
3.6
The minimum erase block is 32 words. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the FLASH array is not
supported.
When initiating an erase sequence from the microcon-
troller itself, a block of 32 words of program memory is
erased.
EEADRH:EEADR point to the block being erased.
EEADR< 4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to setup the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the erase
takes place. This is not SLEEP mode, as the clocks and
peripherals will continue to run. After the erase cycle,
the processor will resume operation with the third
instruction after the EECON1 write instruction.
3.6.1
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
Load EEADRH:EEADR with address of row
being erased.
Set EEPGD bit to point to program memory, set
WREN bit to enable writes, and set FREE bit to
enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase.
Erasing FLASH Program Memory
The
FLASH PROGRAM MEMORY
ERASE SEQUENCE
Most
Significant
 2003 Microchip Technology Inc.
11
bits of
the