PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet
PIC16F88-I/P
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PIC16F88-I/P Summary of contents
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... Microchip Technology Inc. PIC16F87/88 18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS30487B ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... Comparator outputs are externally accessible Program Memory Device FLASH # Single Word SRAM (bytes) Instructions (bytes) PIC16F87 7168 4096 368 PIC16F88 7168 4096 368 2003 Microchip Technology Inc. PIC16F87/88 Pin Diagram 18-Pin DIP, SOIC RA2/AN2/CV RA3/AN3/V RA4/AN4/T0CKI/ RA5/MCLR/V RB0/INT/CCP1 RB1/SDI/SDA ...
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... RB6/PGC/T1OSO/T1CKI 8 13 RB5/SS/TX/ (1) 11 RB4/SCK/SCL RA1/AN1 REF REF +/C1OUT RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO (1) RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI 8 11 RB5/SS/TX/CK (1) RB4/SCK/SCL RA1/AN1 1 20 REF REF +/C1OUT 2 19 RA0/AN0 3 18 RA7/OSC1/CLKI RA6/OSC2/CLKO (1) RB7/AN6/PGD/T1OSI 7 14 RB6/AN5/PGC/T1OSO/T1CKI 8 13 RB5/SS/TX/ (1) RB4/SCK/SCL 11 10 Preliminary 2003 Microchip Technology Inc. ...
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... Pin Diagrams (Cont’d) 28-Pin QFN RA5/MCLR (1) RB0/INT/CCP1 28-Pin QFN RA5/MCLR (1) RB0/INT/CCP1 Note 1: The CCP1 pin is determined by CCPMX in Configuration Word 1 register. 2003 Microchip Technology Inc RA7/OSC1/CLKI 20 2 RA6/OSC2/CLKO PIC16F87 RB7/PGD/T1OSI 15 7 RB6/PGC/T1OSO/T1CKI 21 1 RA7/OSC1/CLKI 2 20 RA6/OSC2/CLKO PIC16F88 RB7/AN6/PGD/T1OSI 7 15 RB6/AN5/PGC/T1OSO/T1CKI Preliminary PIC16F87/88 DS30487B-page 3 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30487B-page 4 Preliminary 2003 Microchip Technology Inc. ...
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... These functions include: • External Interrupt • Change on PORTB Interrupt • Timer0 Clock Input • Low-power Timer1 Clock/Oscillator • Capture/Compare/PWM • 10-bit, 7-channel A/D Converter (PIC16F88 only) 2 • SPI™/I C™ • Two Analog Comparators • USART • MCLR (RA5) can be configured as an Input Table 1-2 details the pinout of the device with descriptions and details for each pin ...
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... FSR reg STATUS reg 3 MUX Timer ALU 8 Reset W reg Timer Reset Timer0 SSP Data EE Comparators 256 Bytes Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/CV REF RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/V PP RA6/OSC2/CLKO RA7/OSC1/CLKI PORTB (2) RB0/INT/CCP1 RB1/SDI/SDA RB2/SDO/RX/DT (2) RB3/PGM/CCP1 RB4/SCK/SCL RB5/SS/TX/CK RB6/PGC/T1OSO/T1CKI RB7/PGD/T1OSI 2003 Microchip Technology Inc. ...
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... FIGURE 1-2: PIC16F88 DEVICE BLOCK DIAGRAM 13 Program Counter FLASH Program Memory 8 Level Stack (13-bit) Program 14 Bus Instruction reg Direct Addr 8 Power-up Timer Oscillator Instruction Start-up Timer Decode & Control Power-on Reset Timing Watchdog Generation Timer OSC1/CLKI Brown-out OSC2/CLKO Reset RA5/MCLR Timer2 ...
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... This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 4: PIC16F88 devices only. 5: The CCP1 pin is determined by CCPMX in Configuration Word 1 register. DS30487B-page 8 QFN I/O/P ...
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... This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 4: PIC16F88 devices only. 5: The CCP1 pin is determined by CCPMX in Configuration Word 1 register. 2003 Microchip Technology Inc. ...
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... PIC16F87/88 NOTES: DS30487B-page 10 Preliminary 2003 Microchip Technology Inc. ...
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... C20h, 1020h, 1420h, 1820h, and 1C20h. The RESET vector is at 0000h and the interrupt vector is at 0004h. 2003 Microchip Technology Inc. PIC16F87/88 FIGURE 2-1: PROGRAM MEMORY MAP AND STACK: PIC16F87/88 PC< ...
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... EECON1 18Ch EECON2 10Dh 18Dh (1) 10Eh Reserved 18Eh (1) 10Fh 18Fh Reserved 110h 190h General Purpose Register 16 Bytes 19Fh 11Fh 1A0h 120h General Purpose Register 80 Bytes 16Fh 1EFh 170h 1F0h accesses 70h - 7Fh 17Fh 1FFh Bank 3 2003 Microchip Technology Inc. ...
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... FIGURE 2-3: PIC16F88 REGISTER FILE MAP File Address (*) Indirect addr. Indirect addr. 00h TMR0 01h OPTION 02h PCL 03h STATUS STATUS FSR 04h 05h PORTA 06h PORTB 07h 08h 09h 0Ah PCLATH PCLATH INTCON 0Bh INTCON PIR1 0Ch 0Dh PIR2 TMR1L ...
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... Indirect Data Memory Address Pointer 05h PORTA PORTA Data Latch when written; PORTA pins when read (PIC16F87) PORTA Data Latch when written; PORTA pins when read (PIC16F88) 06h PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87) PORTB Data Latch when written; PORTB pins when read (PIC16F88) 07h — ...
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... These registers can be addressed from any bank. 3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’. 4: PIC16F88 device only. 2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...
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... These registers can be addressed from any bank. 3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’. 4: PIC16F88 device only. DS30487B-page 16 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged recommended, therefore, that only BCF, BSF, ...
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... Timer (WDT)” for further details. R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... At least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TXIE: USART Transmit Interrupt Enable bit ...
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... ADIF: A/D Converter Interrupt Flag bit 1 = The A/D conversion completed (must be cleared in software The A/D conversion is not complete Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) ...
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... R = Readable bit -n = Value at POR DS30487B-page 22 U-0 R/W-0 U-0 U-0 — EEIE — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2003 Microchip Technology Inc. U-0 U-0 — — bit Bit is unknown ...
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... The write operation completed (must be cleared in software The write operation is not complete or has not been started bit 3-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. U-0 R/W-0 CMIF — EEIF W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... BOREN bit in the Configuration Word register). U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-x — POR BOR bit Bit is unknown 2003 Microchip Technology Inc. ...
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... PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 2003 Microchip Technology Inc. Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP ...
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... FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING ;initialize pointer ;to RAM INDF ;clear INDF register FSR,F ;inc pointer ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 0 FSR Register Location Select 2003 Microchip Technology Inc. ...
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... When code protected, the device programmer can no longer access data or program memory; this does NOT inhibit internal reads or writes. 2003 Microchip Technology Inc. PIC16F87/88 3.1 EEADR and EEADRH The EEADRH:EEADR register pair can address maximum of 256 bytes of data EEPROM maximum of 8K words of program EEPROM ...
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... Value at POR DS30487B-page 28 U-0 U-0 R/W-x R/W-x — — FREE WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ Set only ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown 2003 Microchip Technology Inc. ...
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... EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. 2003 Microchip Technology Inc. PIC16F87/88 The steps to write to EEPROM data memory are step 10 is not implemented, check the WR bit to see if a write is in progress ...
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... WREN bit to enable writes, and set FREE bit to enable the erase. 3. Disable interrupts. 4. Write 55h to EECON2. 5. Write AAh to EECON2. 6. Set the WR bit. This will begin the row erase cycle. 7. The CPU will stall for duration of the erase. Preliminary Significant 11 bits of the 2003 Microchip Technology Inc. ...
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... MOVWF EECON2 BSF EECON1, WR NOP NOP BCF EECON1, WREN BSF INTCON, GIE 2003 Microchip Technology Inc. ; Select Bank of EEADRH ; ; MS Byte of Program Address to Erase ; ; LS Byte of Program Address to Erase ; Select Bank of EECON1 ; Point to PROGRAM memory ; Enable Write to memory ; Enable Row Erase operation ...
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... EEDATH EEDATA EEADR<1:0> Buffer Register Buffer Register Program Memory Preliminary “BSF instruction, EECON1,WR” “BSF instruction, EECON1,WR” transfer the data from 0 All buffers are transferred to FLASH automatically after this word is written 14 EEADR<1:0> Buffer Register 2003 Microchip Technology Inc ...
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... GOTO loop BANKSEL EECON1 BCF EECON1,WREN BSF INTCON,GIE 2003 Microchip Technology Inc. ;prepare for WRITE procedure ;point to program memory ;allow write cycles ;prepare for 4 words to be written ;Start writing at 0x100 ;load HIGH address ;load LOW address ;initialize FSR to start of data ...
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... EEIE — — Preliminary Value on Value on Bit 0 Power-on all other Reset RESETS xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu ---- -xxx ---- -uuu RD x--x x000 x--x q000 ---- ---- ---- ---- — — 00-0 ---- 00-0 ---- — — 00-0 ---- 00-0 ---- 2003 Microchip Technology Inc. ...
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... A series resistor (R ) may be required for AT strip S cut crystals varies with the crystal chosen (typically F between 2003 Microchip Technology Inc. TABLE 4-1: Osc Type Capacitor values are for design guidance only. These capacitors were tested with the crystals listed /4 OSC below for basic start-up and operation ...
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... PORTA (RA6). Figure 4-3 shows the pin connections for the ECIO Oscillator mode. To Internal Logic FIGURE 4-3: Clock from Ext. System . OSC2 for DD is 330 Preliminary EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC16F87/88 I/O (OSC2) RA6 2003 Microchip Technology Inc. ...
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... RA6 Recommended values EXT C > EXT 2003 Microchip Technology Inc. 4.5 Internal Oscillator Block The PIC16F87/88 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This ) val- can eliminate the need for external oscillator circuits on EXT the OSC1 and/or OSC2 pins ...
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... U-0 R/W-0 R/W-0 R/W-0 — TUN5 TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in Power Managed modes. When the bits are cleared (SCS<1:0> = 00), the system clock source comes from the main oscillator that is selected by the 2003 Microchip Technology Inc. PIC16F87/88 F 2:F 0 configuration bits in Configuration Regis- ...
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... R/W-0 R/W-0 R-0 R/W-0 (1) IRCF1 IRCF0 OSTS IOFS (1) <2:0> OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2003 Microchip Technology Inc. R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown ...
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... Caution must be taken when modifying the IRCF bits using BCF or BSF instructions possible to modify the IRCF bits to a fre- quency that may be out of the V cation range; for example, V IRCF = 111 (8 MHz). 2003 Microchip Technology Inc. LP, XT, HS, RC Timer1 OSCCON<6:4> 8 MHz 111 ...
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... POR, CPU start-up is invoked to allow the (1) CPU Start-up CPU to become ready for code execution. 1024 Clock Cycles Following a change from INTRC, an OST (OST) of 1024 cycles must occur Refer to Section 4.6.4 “Modifying the IRCF bits” for further details. Preliminary 2003 Microchip Technology Inc. Comments ...
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... DLY INP 2003 Microchip Technology Inc. PIC16F87/88 If the system clock does not come from the INTRC (31.25 kHz) when the SCS bits are changed, and the IRCF bits in the OSCCON register are configured for a frequency other than INTRC, the frequency may not be stable immediately. The IOFS bit (OSCCON< ...
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... When T1OSCEN = 0, the following possible effects result. Original SCS<1:0> clock switching event will occur if the final state of the SCS bits is different from the original (3) T SCS PC +1 Preliminary Modified Final SCS<1:0> SCS<1:0> change INTRC change OSC 01 defined by F <2:0> OSC 2003 Microchip Technology Inc. ...
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... If the primary system clock is either RC or EC, an internal delay timer (5-10 s) will suspend operation after exiting Secondary Clock mode to allow the CPU to become ready for code execution. 2003 Microchip Technology Inc. 4.7.3.1 Returning to Primary Clock Source Sequence Changing back to the primary oscillator from SEC_RUN or RC_RUN can be accomplished by either changing SCS< ...
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... TIMING FOR TRANSITION BETWEEN SEC_RUN/RC_RUN AND PRIMARY CLOCK Sec. Osc OSC1 T OST OSC2 Primary Clock System Clock SCS<1:0> OSTS Program Counter Note 30. typical. INP minimum. OSC SCS INP DLY INP DS30487B-page 46 P (1) INP ( SCS (4) OSC ( (5) T DLY Preliminary 2003 Microchip Technology Inc. ...
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... OSC 5- MHz system clock). CPU 2003 Microchip Technology Inc. there is no oscillator start-up time required because the primary clock is already stable; however, there is a delay between the wake-up event and the following Q2. An internal delay timer of 5-10 s will suspend operation after the RESET to allow the CPU to become ready for code execution ...
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... PIC16F87/88 FIGURE 4-11: PRIMARY SYSTEM CLOCK AFTER RESET (EC, RC, INTRC T1OSI OSC1 OSC2 CPU (2) T CPU Start-up System Clock MCLR OSTS Program PC Counter Note 30. MHz system clock). CPU DS30487B-page 0001h 0002h 0000h Preliminary 0003h 0004h 2003 Microchip Technology Inc. ...
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... Clocks of LP, XT, HS LP, XT, HS 1024 Clocks 00 (Due to RESET) LP, XT, HS Note 1: If the new clock source is INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms after the clock change. 2003 Microchip Technology Inc. OSTS IOFS T1RUN Delay bit bit bit (1) ...
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... XT, LP, or HS, the core will continue to run off T1OSC and execute the SLEEP command. When SLEEP is exited, the part will resume operation oscillator after the OST has expired. Preliminary 2003 Microchip Technology Inc. OSCCON,SCS0 with the primary ...
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... Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 2: PIC16F88 only. 2003 Microchip Technology Inc. Pin RA4 is multiplexed with the Timer0 module clock input and with analog input to become the RA4/AN4/ T0CKI/C2OUT pin ...
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... Shaded cells are not used by PORTA. Note 1: This value applies only to the PIC16F87. 2: This value applies only to the PIC16F88. 3: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. 4: PIC16F88 device only ...
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... Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA To Comparator To A/D Module V - (PIC16F88 only) REF To A/D Module Channel Input (PIC16F88 only) 2003 Microchip Technology Inc. +/C1OUT PIN REF Comparator Mode = 110 Analog Input Mode Q + Input (PIC16F88 only) REF /V - PIN REF REF ...
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... Q Comparator 2 Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA TMR0 Clock Input To A/D Module Channel Input (PIC16F88 only) FIGURE 5-5: BLOCK DIAGRAM OF RA5/MCLR/V MCLRE MCLR Circuit Data Bus V RD TRIS SS RD Port DS30487B-page Analog Input Mode Q EN PIN ...
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... OSC Data Bus PORTA CK Q Data Latch TRISA TRIS Latch RD TRISA Q RD PORTA Note 1: I/O pins have protection diodes CLKO signal is 1/4 of the F 2003 Microchip Technology Inc. From OSC1 Oscillator Circuit 1x0, 011) OSC V SS Schmitt Trigger Input Buffer 1x0, 011) ...
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... Data Latch TRISA CK Q TRIS Latch RD TRISA Q RD PORTA Note 1: I/O pins have protection diodes to V DS30487B-page 56 Oscillator Circuit (F = 011) OSC 10x OSC V SS Schmitt Trigger Input Buffer 10x OSC and Preliminary V DD (1) RA7/OSC1/CLKI pin V SS 2003 Microchip Technology Inc. ...
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... Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF. 2003 Microchip Technology Inc. PIC16F87/88 A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. ...
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... INTEDG T0CS T0SE PSA (1) 9Bh ANSEL — ANS6 Legend unknown unchanged. Shaded cells are not used by PORTB. Note 1: PIC16F88 device only. DS30487B-page 58 Function (1) Input/output pin or external interrupt input. Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up. (5) Input/output pin, SPI data input pin or I Internal software programmable weak pull-up ...
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... CCP1<M3:M0> = 1000, 1001, 11xx and CCPMX = 1 CCP (2) RBPU Data Bus WR PORTB WR TRISB To INT0 or CCP Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2003 Microchip Technology Inc. 0 CCP1<M3:M0> = 000 1 Data Latch TRIS Latch D ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SDA Schmitt conforms to the I DS30487B-page TRISB Q Schmitt Trigger Buffer and specification. Preliminary V DD Weak P Pull- (1) I/O pin TTL Input Buffer PORTB 2003 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RB2 PIN SSPEN SDO 1 0 RBPU Data Bus WR PORTB WR TRISB DT Drive RX/DT Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2003 Microchip Technology Inc. SPEN (2) Data Latch TRIS Latch ...
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... I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30487B-page 62 CCP1<M3:M0> = 0100, 0101, 0110, 0111 and CCPMX = LVP = Weak P Pull-up (1) I/O pin TTL Input Buffer PORTB and Preliminary 2003 Microchip Technology Inc. ...
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... RD PORTB Set RBIF From Other RB7:RB4 pins SCK SCL Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SCL Schmitt conforms to the I 2003 Microchip Technology Inc SCL Drive (3) and ...
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... I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30487B-page 64 Data Latch TRIS Latch Latch Q Q and Preliminary V DD Weak P Pull-up (1) I/O pin TTL Input Buffer PORTB EN Q3 2003 Microchip Technology Inc. ...
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... Mode Set RBIF From other RB7:RB4 pins PGC/T1CKI From T1OSCO Output To A/D Module Channel Input (PIC16F88 only) Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2003 Microchip Technology Inc. ...
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... TRISB RD TRISB T1OSCEN PGD DRVEN RD PORTB Set RBIF From Other RB7:RB4 pins PGD To T1OSCI Input To A/D Module Channel Input (PIC16F88 only) Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30487B-page ...
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... Prescaler WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). 2003 Microchip Technology Inc. increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION< ...
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... U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ® Mid-Range MCU Family Reference Manual (DS33023) must be exe- Preliminary to Timer0, will clear the R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... GIE PEIE 10Bh,18Bh 81h,181h OPTION RBPU INTEDG Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. 2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x T0CS ...
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... PIC16F87/88 NOTES: DS30487B-page 70 Preliminary 2003 Microchip Technology Inc. ...
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... Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. 2003 Microchip Technology Inc. PIC16F87/88 7.1 Timer1 Operation Timer1 can operate in one of three modes: • ...
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... Value at POR DS30487B-page 72 R-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... TMR1H T1OSC T1OSO/T1CKI T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. 2003 Microchip Technology Inc. 7.4 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of ...
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... This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. The example codes provided Example 7-2 demonstrate how to write to and read Timer1 while it is running in Asynchronous mode. Preliminary 2003 Microchip Technology Inc. in Example 7-1 and ...
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... Capacitor values are for design guidance only. 2003 Microchip Technology Inc. 7.7 Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power dur- ing operation. Due to the low-power nature of the oscil- lator, it may also be sensitive to rapidly changing signals in close proximity ...
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... For this method to be accurate, Timer1 must operate in Asynchronous mode, and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the rou- tine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary 2003 Microchip Technology Inc. ...
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... T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2003 Microchip Technology Inc. ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
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... PIC16F87/88 NOTES: DS30487B-page 78 Preliminary 2003 Microchip Technology Inc. ...
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... Additional information on timer modules is available in ® the PICmicro Mid-Range MCU Family Reference Manual (DS33023). 2003 Microchip Technology Inc. 8.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • A write to the TMR2 register • ...
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... Bit is unknown Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF -000 0000 -000 0000 TMR2IE TMR1IE -000 0000 -000 0000 0000 0000 0000 0000 1111 1111 1111 1111 2003 Microchip Technology Inc. ...
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... TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. The CCP module’s input/output pin (CCP1) can be configured as RB0 or RB3. This selection is set in bit 12 (CCPMX) of the configuration word. Additional information on the CCP module is available ® ...
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... EXAMPLE 9-1: CLRF CCP1CON MOVLW NEW_CAPT_PS ;Load the W reg with MOVWF CCP1CON CCPR1L TMR1L Preliminary CHANGING BETWEEN CAPTURE PRESCALERS ;Turn CCP module off ;the new prescaler ;move value and CCP ON ;Load CCP1CON with this ;value 2003 Microchip Technology Inc. ...
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... CCP1CON — — Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. 2003 Microchip Technology Inc. 9.2.1 CCP PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the TRISB<x> bit. ...
Page 86
... PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Preliminary • OSC (TMR2 prescale value) T • (TMR2 prescale value) OSC 2003 Microchip Technology Inc. ...
Page 87
... CCP1CON Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. 2003 Microchip Technology Inc. 9.3.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
Page 88
... PIC16F87/88 NOTES: DS30487B-page 86 Preliminary 2003 Microchip Technology Inc. ...
Page 89
... Family Reference (DS33023). Refer to Application Note AN578, “Use of the SSP 2 Module in the I C™ Multi-Master Environment” (DS00578). 2003 Microchip Technology Inc. 10.2 SPI Mode This section contains operational characteristics of the SPI module. SPI mode allows 8 bits of data to be synchronously ...
Page 90
... C mode only mode only mode only mode only modes): C mode only Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-0 (1) R bit 0 ® Bit is unknown 2003 Microchip Technology Inc. ...
Page 91
... C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled 1000, 1001, 1010, 1100, 1101 = Reserved Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) SSPEN CKP SSPM3 ...
Page 92
... P S R/W Preliminary . DD Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS INTF RBIF 0000 000x 0000 000u 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 UA BF 0000 0000 0000 0000 2003 Microchip Technology Inc. ...
Page 93
... SSPIF FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 SDI (SMP = 0) bit 7 SSPIF 2003 Microchip Technology Inc. bit 6 bit 5 bit 3 bit 4 bit 6 bit 5 bit 3 bit 4 bit 2 bit 5 bit 4 bit 3 Preliminary ...
Page 94
... The high and low times of the specification, as well as the requirement of the SSP module, are shown in timing parameter #100 and parameter #101. Preliminary 2 C opera modes to be selected mode, with the SSPEN bit set module operation may be ® Mid-Range MCU Reference 2003 Microchip Technology Inc. ...
Page 95
... Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 2003 Microchip Technology Inc. PIC16F87/88 10.3.1.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared ...
Page 96
... CKP bit can be set) Preliminary Set bit SSPIF (SSP Interrupt Occurs if Enabled) Yes Yes Yes Yes Receiving Data ACK Bus master terminates transfer ACK is not sent Transmitting Data ACK From SSP Interrupt Service Routine 2003 Microchip Technology Inc. ...
Page 97
... Shaded cells are not used by SSP module in SPI mode. 2 Note 1: Maintain these bits clear mode. 2003 Microchip Technology Inc. 10.3.3 MULTI-MASTER MODE OPERATION In Multi-Master mode operation, the interrupt genera- tion on the detection of the START and STOP condi- tions allows the determination of when the bus is free. ...
Page 98
... PIC16F87/88 NOTES: DS30487B-page 96 Preliminary 2003 Microchip Technology Inc. ...
Page 99
... TX9D: 9th bit of Transmit Data, can be Parity bit Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous - Master (half-duplex) • Synchronous - Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISB<5,2> have to ...
Page 100
... Value at POR DS30487B-page 98 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 101
... SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as ‘0’. Shaded cells are not used by the BRG. 2003 Microchip Technology Inc. 11.1.1 USART AND INTRC OPERATION The PIC16F87/88 has an 8 MHz INTRC that can be used as the system clock, thereby eliminating the need for external components to provide the clock source ...
Page 102
... Preliminary = 10 MHz SPBRG % value (decimal) — — 129 — 255 — MHz SPBRG % value (decimal) — — — — 255 64 31 -1.36 21 -2.10 18 -1.36 10 — 255 — 0 2003 Microchip Technology Inc. ...
Page 103
... Microchip Technology Inc MHz MHz OSC OSC SPBRG % % value ERROR KBAUD ERROR (decimal) 0 207 0.300 0 +0.16 51 1.202 +0.16 +0. ...
Page 104
... TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register. Data Bus TXREG Register 8 LSb Pin Buffer 0 and Control TSR Register TRMT TX9 TX9D Preliminary RB5/SS/TX/CK pin SPEN 2003 Microchip Technology Inc. ...
Page 105
... TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. 2003 Microchip Technology Inc 9-bit transmission is desired, then set transmit bit TX9. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF ...
Page 106
... RCIF Interrupt RCIE START bit 7/8 bit 7/8 STOP STOP bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Preliminary FERR RSR Register LSb 1 0 START RCREG Register FIFO 8 Data Bus START bit bit 7/8 STOP bit 2003 Microchip Technology Inc. ...
Page 107
... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. 2003 Microchip Technology Inc. 6. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated if enable bit RCIE is set. ...
Page 108
... CPU. OERR CREN 64 RSR Register MSb STOP (8) Data RX9 Recovery Enable Load of Receive Buffer RX9D RCREG Register 8 RCIF Interrupt RCIE Preliminary 2003 Microchip Technology Inc. FERR LSb 0 1 START 8 8 FIFO Data Bus ...
Page 109
... TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. 2003 Microchip Technology Inc. START bit 8 bit 8 STOP bit bit 0 bit Bit Address Byte START ...
Page 110
... Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Preliminary 2003 Microchip Technology Inc. ...
Page 111
... Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 11-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RB2/SDO/RX/DT pin RB5/SS/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit 2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TMR0IE INTE RBIE TMR0IF ...
Page 112
... Preliminary Value on Value on: Bit 0 all other POR, BOR RESETS R0IF 0000 000x 0000 000u -000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 -000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2003 Microchip Technology Inc. ...
Page 113
... TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. 2003 Microchip Technology Inc Q4Q1 Q4Q1 Q4Q1 bit 1 bit 2 bit 3 bit 4 bit enable bit TXIE is set, the interrupt will wake ...
Page 114
... SYNC — BRGH TRMT Preliminary Value on Value on: Bit 0 all other POR, BOR RESETS R0IF 0000 000x 0000 000u RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2003 Microchip Technology Inc. ...
Page 115
... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has seven inputs for 18/20 pin devices (PIC16F88 devices only). The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has a high and low voltage reference input that is soft- ...
Page 116
... PIC16F87/88 REGISTER 12-2: ADCON0 REGISTER (ADDRESS 1Fh) PIC16F88 DEVICES ONLY R/W-0 R/W-0 ADCS1 ADCS0 bit 7 bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits If ADSC2 = OSC OSC /32 OSC (clock derived from the internal A/D module RC oscillator ADSC2 = OSC /16 OSC /64 OSC (clock derived from the internal A/D module RC oscillator) ...
Page 117
... REGISTER 12-3: ADCON1 REGISTER (ADDRESS 9Fh) PIC16F88 DEVICES ONLY R/W-0 R/W-0 ADFM ADCS2 bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’ Left justified. Six Least Significant bits of ADRESL are read as ‘0’. ...
Page 118
... The A/D conversion time per bit is defined as T required before the next acquisition starts. CHS2:CHS0 110 101 100 011 010 V IN 001 000 AV DD VCFG1:VCFG0 AV SS VCFG1:VCFG0 Preliminary . A minimum wait RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI RA4/AN4/T0CKI/C2OUT RA3/AN3/V +/C1OUT REF RA2/AN2/ REF REF RA1/AN1 RA0/AN0 2003 Microchip Technology Inc. ...
Page 119
... sampling switch C = sample/hold capacitance (from DAC) HOLD 2003 Microchip Technology Inc. may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution ...
Page 120
... RA4:RA0 and RB7:RB6 pins), may cause the input buffer to consume current out of the device specification ADCS<1:0> time but can vary between 2 Preliminary Maximum Device Frequency Max. 1.25 MHz 2.5 MHz 5 MHz 10 MHz 20 MHz 20 MHz (Note 1) 2003 Microchip Technology Inc. ...
Page 121
... ADRESH ADRESL 10-bit Result Right Justified 2003 Microchip Technology Inc. 12.4.1 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16 bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register ...
Page 122
... TRISB TRISB7 TRISB6 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: PIC16F88 only. 2: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. DS30487B-page 120 12.6 ...
Page 123
... RA1 IN bit 2-0 CM<2:0>: Comparator Mode bits Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. The CMCON register (Register 13-1) controls the com- parator input and output multiplexers. A block diagram two analog of the various comparator configurations is shown in Figure 13-1. ...
Page 124
... Three Inputs Multiplexed to Two Comparators CM2:CM0 = 001 A RA0/AN0 (Read as ‘0’) A RA3/AN3 A RA1/AN1 A RA2/AN2 Preliminary Off C1 (Read as ‘0’ Off C2 (Read as ‘0’ CIS = CIS = 1 C1OUT CIS = CIS = 1 C2OUT From V Module REF C1OUT C2OUT CIS = CIS = 1 C1OUT C2OUT 2003 Microchip Technology Inc. ...
Page 125
... The reference signal must be between V and V , and can be applied to either SS DD pin of the comparator(s). 2003 Microchip Technology Inc. 13.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated comparators. Section 14.0 “Comparator Voltage ...
Page 126
... Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared. Preliminary Port Pins MULTIPLEX CnINV RD_CMCON 2003 Microchip Technology Inc. ...
Page 127
... R = Interconnect Resistance Source Impedance Analog Voltage 2003 Microchip Technology Inc. PIC16F87/88 13.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 13-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V ...
Page 128
... PIE2 OSFIE CMIE 05h PORTA RA7 RA6 (PIC16F87) (PIC16F88) 85h TRISA TRISA7 TRISA6 TRISA5 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. ...
Page 129
... When CVRR = 1/4 (CV REF Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. supply voltage (also referred directly from V voltage at the top of the ladder is CV where V is the saturation voltage of the power SAT switch transistor. This reference will only be as accurate as the values of CV ’ ...
Page 130
... Bit 2 Bit 1 CVRR — CVR3 CVR2 CVR1 C2INV C1INV CIS CM2 CM1 Preliminary R 8R CVRR CVR3 CVR2 CVR1 CVR0 Value on Value on Bit 0 all other POR RESETS CVR0 000- 0000 000- 0000 CM0 0000 0111 0000 0111 2003 Microchip Technology Inc. ...
Page 131
... RESET while the power supply stabilizes, and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external RESET circuitry. 2003 Microchip Technology Inc. PIC16F87/88 SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt ...
Page 132
... R/P-1 R/P-1 R/P-1 CPD LVP BOREN MCLRE F 2 PWRTEN WDTEN F OSC Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/P-1 R/P-1 R/P-1 R/P OSC OSC bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 133
... Internal External Switch Over mode enabled 0 = Internal External Switch Over mode disabled bit 0 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. U-1 U-1 U-1 U-1 U-1 — — — ...
Page 134
... This delay runs in parallel with any other timers. See Table 15-4 for a full description of RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 15-1. Preliminary 2003 Microchip Technology Inc. S Chip_Reset R Q Enable PWRT Enable OST ...
Page 135
... V is specified. See Section 18.0 “Electrical DD Characteristics” for details. 2003 Microchip Technology Inc. When the device starts normal operation (exits the RESET condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met ...
Page 136
... Brown-out Reset 1 WDT Reset 1 WDT Wake-up 0 MCLR Reset during normal operation u MCLR Reset during SLEEP or interrupt wake-up from SLEEP 0 Preliminary Wake-up from SLEEP PWRTE = 1 1024 • T 1024 • T OSC OSC (1) (1) 5-10 s 5-10 s (1) — 5-10 s 2003 Microchip Technology Inc. ...
Page 137
... W xxxx xxxx INDF TMR0 xxxx xxxx PCL 0000h STATUS 0001 1xxx FSR xxxx xxxx PORTA (PIC16F87) xxxx 0000 PORTA (PIC16F88) xxx0 0000 PORTB (PIC16F87) xxxx xxxx PORTB (PIC16F87) 00xx xxxx PCLATH ---0 0000 INTCON 0000 000x PIR1 -000 0000 PIR2 00-0 ---- ...
Page 138
... Preliminary 2003 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uu-u ---- ...
Page 139
... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 15-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK): CASE MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2003 Microchip Technology Inc. PIC16F87/88 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary THROUGH ...
Page 140
... Q cycle. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit or the GIE bit. Preliminary 2003 Microchip Technology Inc. ...
Page 141
... OSFIF OSFIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CMIF CMIE 2003 Microchip Technology Inc. PIC16F87/88 TMR0IF TMR0IE INTF INTE RBIF RBIE PEIE GIE Preliminary Wake-up (If in SLEEP mode) Interrupt to CPU DS30487B-page 139 ...
Page 142
... PIC16F87/88 devices, temporary holding registers W_TEMP, STATUS_TEMP, should be placed in here. These 16 locations don’t require banking and therefore, make it easier for con- text save and restore. The same code shown in Example 15-1 can be used. Preliminary 2003 Microchip Technology Inc. and PCLATH_TEMP ...
Page 143
... Programmable Prescaler WDT 31.25 kHz INTRC Clock WDTEN from Configuration Word SWDTEN from WDTCON 2003 Microchip Technology Inc. 15.12.2 WDT CONTROL The WDTEN bit is located in Configuration Word 1 and when this bit is set, the WDT runs continuously. The SWDTEN bit is in the WDTCON register. When the WDTEN bit in the Configuration Word 1 register is set, the SWDTEN bit has no effect ...
Page 144
... T0SE PSA BOREN MVCLRE F 2 PWRTEN OSC — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN Preliminary Postscaler (PSA = 1) Cleared Cleared at end of OST R/W-0 R/W-0 R/W-0 (1) bit 0 ( Bit is unknown Bit 2 Bit 1 Bit 0 PS2 PS1 PS0 WDTEN OSC OSC 2003 Microchip Technology Inc. ...
Page 145
... SLEEP OSTS Program PC Counter 2003 Microchip Technology Inc. Checking the state of the OSTS bit will confirm whether the primary clock configuration is engaged. If not, the OSTS bit will remain clear. When the device is auto-configured in INTRC mode fol- lowing a POR or wake-up from SLEEP, the rules for entering other oscillator modes still apply, meaning the SCS< ...
Page 146
... T1OSC, INTRC, or none (SLEEP mode). However, the FSCM will continue to monitor the sys- tem clock. If the secondary clock fails, the device will immediately switch to the internal oscillator clock. If OSFIE is set, an interrupt will be generated. Oscillator Failure CM Test Preliminary Failure Detected CM Test 2003 Microchip Technology Inc. ...
Page 147
... Monitoring the OSTS bit will determine if the crystal is operating. The user should not enter SLEEP mode without handling the fail-safe condition first. 2003 Microchip Technology Inc. PIC16F87/88 2. CONDITIONS: After a POR (Power-on Reset), the device is running in Two-Speed Start-up mode ...
Page 148
... NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction (2) T OST Interrupt Latency (Note 2) Processor in SLEEP PC+2 PC Inst( Dummy Cycle Inst( Preliminary (1) 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) 2003 Microchip Technology Inc. ...
Page 149
... It is recom- mended that only the four Least Significant bits of the ID location are used. 2003 Microchip Technology Inc. 15.17 In-Circuit Serial Programming PIC16F87/88 microcontrollers can be serially pro- grammed while in the end application circuit. This is ...
Page 150
... PIC16F87/88 device will enter Programming mode. 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be disabled by clearing the LVP bit in the CONFIG register. 6: Disabling LVP will provide maximum compatibility devices. Preliminary 2003 Microchip Technology Inc. to the IHH ICSP mode to other PIC16CXXX ...
Page 151
... A read operation is performed on a register even if the instruction writes to that register. 2003 Microchip Technology Inc. For example, a “clrf PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- tended result that the condition that sets the RBIF flag would be cleared ...
Page 152
... TO PD 0000 0110 0100 , 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO PD 0000 0110 0011 , C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk ® Mid-Range MCU 2003 Microchip Technology Inc. ...
Page 153
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. 2003 Microchip Technology Inc. ANDWF k Syntax: Operands: Operation: Status Affected: Description: BCF Syntax: f,d Operands: ...
Page 154
... None 00h ( register is cleared. Zero bit (Z) is set. Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. 2003 Microchip Technology Inc. ...
Page 155
... W register. If ‘d’ the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making instruction. CY 2003 Microchip Technology Inc. PIC16F87/88 GOTO Unconditional Branch Syntax: [ label ] Operands Operation: k PC< ...
Page 156
... The eight-bit literal ‘k’ is loaded into W register. The don’t cares will assemble as ‘0’s. Move label ] MOVWF 127 (W) (f) None Move data from W register to register ‘f’. No Operation [ label ] NOP None No operation None No operation. 2003 Microchip Technology Inc. ...
Page 157
... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. 2003 Microchip Technology Inc. PIC16F87/88 RLF Rotate Left f through Carry Syntax: [ label ] Operands [0,1] ...
Page 158
... Operation: (W) .XOR. (f) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’. Preliminary 2003 Microchip Technology Inc. XORLW k 255 W) f,d 127 destination) ...
Page 159
... OQ - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2003 Microchip Technology Inc. PIC16F87/88 17.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 160
... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary economical software 2003 Microchip Technology Inc. ...
Page 161
... The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 2003 Microchip Technology Inc. PIC16F87/88 17.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 162
... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion. Preliminary 2003 Microchip Technology Inc. ...
Page 163
... Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices. 2003 Microchip Technology Inc. 17.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 164
... PIC16F87/88 NOTES: DS30487B-page 162 Preliminary 2003 Microchip Technology Inc. ...
Page 165
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2003 Microchip Technology Inc. (except V and MCLR) ................................................... -0. (Note 2) ...
Page 166
... F = (12 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10 MHz. MAX DS30487B-page 164 16 MHz Frequency 4 MHz 10 MHz Frequency – 2.5V MHz DDAPPMIN ® Preliminary 20 MHz device in the application. 2003 Microchip Technology Inc. ...
Page 167
... Note 1: This is the limit to which V can be lowered in SLEEP mode, or during a device RESET, without losing RAM data When BOR is enabled, the device will operate correctly until the V 2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 168
... A 25° 1.7 A 85°C 1.0 A -40°C 1.0 A 25° 5.0 A 85°C is not included. The current through the resistor can be estimated EXT (mA) with EXT Preliminary Conditions = 2.0V = 3. and all features that add delta 2003 Microchip Technology Inc. ...
Page 169
... OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V MCLR = V ; WDT enabled/disabled as specified For RC oscillator configurations, current through R by the formula /2R DD EXT 2003 Microchip Technology Inc. -40°C T +85°C for industrial A -40°C T +85°C for industrial A Max ...
Page 170
... V DD 2.2 mA 85°C 4.2 mA -40°C 4.0 mA 25° 4.0 mA 85°C is not included. The current through the resistor can be estimated EXT (mA) with EXT Preliminary Conditions = 4. OSC Z (HS Oscillator and all features that add delta 2003 Microchip Technology Inc. ...
Page 171
... OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V MCLR = V ; WDT enabled/disabled as specified For RC oscillator configurations, current through R by the formula /2R DD EXT 2003 Microchip Technology Inc. -40°C T +85°C for industrial A -40°C T +85°C for industrial A Max ...
Page 172
... A 70°C is not included. The current through the resistor can be estimated EXT (mA) with EXT Preliminary Conditions = 3. MHz OSC (RC_RUN mode, Internal RC Oscillator) = 5. kHz OSC = 3.0V (SEC_RUN mode, Timer1 as clock and all features that add delta 2003 Microchip Technology Inc. ...
Page 173
... OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V MCLR = V ; WDT enabled/disabled as specified For RC oscillator configurations, current through R by the formula /2R DD EXT 2003 Microchip Technology Inc. -40°C T +85°C for industrial A -40°C T +85°C for industrial A Max ...
Page 174
... Conditions (1) 25° 2.7-3.3V DD -10°C - +85° 2.7-3.3V DD -40°C - +85° 2.7-3.3V DD 25° 4.5-5.5V DD -10°C - +85° 4.5-5.5V DD -40°C - +85° 4.5-5.5V DD -40°C - +85° 2.7-3.3V DD -40°C - +85° 4.5-5.5V DD 2003 Microchip Technology Inc. ...
Page 175
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2003 Microchip Technology Inc. PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) ...
Page 176
... C to +125 -1.3 mA 4.5V - +125 XT, HS and LP modes when external clock is used to drive OSC1 pF pF E/W - E/W + +125 C V Using EECON to read/write min. operating voltage MIN 8 ms E/W - E/W + +125 Using EECON to read/write min. operating voltage MIN 2003 Microchip Technology Inc. ...
Page 177
... Unit Resistor Value (R)* 310 (1)* Settling Time * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2003 Microchip Technology Inc. < +85°C, unless otherwise stated. A Sym Min Typ Max V — ...
Page 178
... OSC2, but including PORTD and PORTE outputs as ports for OSC2 output DS30487B-page 176 specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance High High Low Low SU Setup STO STOP condition Load Condition Pin V SS Preliminary 2003 Microchip Technology Inc. ...
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... All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 2003 Microchip Technology Inc ...
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... (Note 1) CY — — ns (Note 1) — — ns (Note 1) 100 255 ns — — ns — — ns — — — 145 — 145 ns — — ns — — ns 2003 Microchip Technology Inc. ...
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... Brown-out Reset Pulse Width BOR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. PIC16F87/ BOR ...
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... CY N PIC16LF87/88 Greater of PIC16F87/88 60 — — PIC16LF87/88 100 — — DC — 32.768 2 T — OSC Preliminary 2003 Microchip Technology Inc. 48 Units Conditions ns Must also meet parameter Must also meet parameter prescale value (2, 4, ..., 256) ns Must also meet parameter Must also meet ...
Page 183
... TccF CCP1 Output Fall Time * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc Min 0.5 T ...
Page 184
... SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb In 74 Note: Refer to Figure 18-3 for load conditions. DS30487B-page 182 MSb Bit 75, 76 Bit LSb Bit 75, 76 Bit LSb In Preliminary 79 78 LSb LSb 2003 Microchip Technology Inc. ...
Page 185
... FIGURE 18-13: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb In 74 Note: Refer to Figure 18-3 for load conditions. 2003 Microchip Technology Inc Bit MSb 75, 76 Bit LSb Bit 75, 76 Bit LSb In Preliminary PIC16F87/88 ...
Page 186
... PIC16LF87/88 — — PIC16F87/88 — PIC16LF87/88 — — 1 Preliminary Typ† Max Units Conditions — — — — — — ns — — ns — — — — — 145 ns — — ns — — — STOP Condition 2003 Microchip Technology Inc. ...
Page 187
... C BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 18-3 for load conditions. 2003 Microchip Technology Inc. Min Typ Max Units 100 kHz mode 4700 — — ns 400 kHz mode 600 — — 100 kHz mode 4000 — ...
Page 188
... C is specified to be from 400 pF s Only relevant for Repeated START s condition s After this period, the first clock pulse is generated (Note (Note Time the bus must be free before a new transmission s can start bus system, but the 2003 Microchip Technology Inc. ...
Page 189
... Data setup before CK (DT setup time) 126 TckL2dtl Data hold after CK (DT hold time) † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. 121 Characteristic Min PIC16F87/88 — ...
Page 190
... REF — AIN REF V -40°C to +85°C V 0°C to +85° See (Note 4) A During V acquisition. AIN Based on differential HOLD V to charge C , see AIN HOLD Section 12.1 “A/D Acquisition Requirements”. A During A/D Conversion cycle. 2003 Microchip Technology Inc. ...
Page 191
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 12.1 “A/D Acquisition Requirements” for minimum conditions. 2003 Microchip Technology Inc. (1) 131 130 8 7 ...
Page 192
... PIC16F87/88 NOTES: DS30487B-page 190 Preliminary 2003 Microchip Technology Inc. ...
Page 193
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES No Graphs and Tables are available at this time. 2003 Microchip Technology Inc. PIC16F87/88 Preliminary DS30487B-page 191 ...
Page 194
... PIC16F87/88 NOTES: DS30487B-page 192 Preliminary 2003 Microchip Technology Inc. ...
Page 195
... Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2003 Microchip Technology Inc. PIC16F87/88 Example PIC16F87/88-I/P ...
Page 196
... L p MILLIMETERS MIN NOM MAX 18 2.54 3.56 3.94 4.32 2.92 3.30 3.68 0.38 7.62 7.94 8.26 6.10 6.35 6.60 22.61 22.80 22.99 3.18 3.30 3.43 0.20 0.29 0.38 1.14 1.46 1.78 0.36 0.46 0.56 7.87 9.40 10. 2003 Microchip Technology Inc. ...
Page 197
... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 2003 Microchip Technology Inc Units INCHES* ...
Page 198
... Preliminary A2 MILLIMETERS MIN NOM MAX 20 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.18 5.11 5.25 5.38 7.06 7.20 7.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0. 2003 Microchip Technology Inc. ...
Page 199
... Tie Bar Length Chamfer Mold Draft Angle Top *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: mMO-220 Drawing No. C04-114 2003 Microchip Technology Inc. EXPOSED METAL PADS ...
Page 200
... PIC16F87/88 NOTES: DS30487B-page 198 Preliminary 2003 Microchip Technology Inc. ...