M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 79

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
Parallel I/O features, depending on package choice, include:
6.3
The MC9S08GB/GT has a total of 56 parallel I/O pins (one is output only) in seven 8-bit ports
(PTA–PTG). Not all pins are bonded out in all packages. Consult the pin assignment in
and
when they are not used by other on-chip peripheral systems.
After reset, BKGD/MS is enabled and therefore is not usable as an output pin until BKGDPE in SOPT is
cleared. The rest of the peripheral functions are disabled. After reset, all data direction and pullup enable
controls are set to 0s. These pins default to being high-impedance inputs with on-chip pullup devices
disabled.
The following paragraphs discuss each port and the software controls that determine each pin’s use.
6.3.1
Port A is an 8-bit port shared among the KBI keyboard interrupt inputs and general-purpose I/O. Any pins
enabled as KBI inputs will be forced to act as inputs.
Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction
(PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to
I/O
Freescale Semiconductor
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Controls,”
Connections,” for available parallel I/O pins. All of these pins are available for general-purpose I/O
Port A
A total of 56 general-purpose I/O pins in seven ports (PTG0 is output only)
High-current drivers on port C and port F pins
Hysteresis input buffers
Software-controlled pullups on each input pin
Software-controlled slew rate output buffers
Eight port A pins shared with KBI1
Eight port B pins shared with ATD1
Eight high-current port C pins shared with SCI2 and IIC1
Eight port D pins shared with TPM1 and TPM2
Eight port E pins shared with SCI1 and SPI1
Eight high-current port F pins
Eight port G pins shared with EXTAL, XTAL, and BKGD/MS
Features
Pin Descriptions
Port A and Keyboard Interrupts
for more information about general-purpose I/O control.
MCU Pin:
KBI1P7
PTA7/
Bit 7
MC9S08GB/GT Data Sheet, Rev. 2.3
KBI1P6
PTA6/
Figure 6-2. Port A Pin Names
6
KBI1P5
PTA5/
5
KBI1P4
PTA4/
4
KBI1P3
PTA3/
3
KBI1P2
PTA2/
2
KBI1P1
PTA1/
Section 6.4, “Parallel
1
Chapter 2, “Pins
KBI1P0
PTA0/
Bit 0
Features
79