M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 110

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Internal Clock Generator (ICG) Module
When the ICG is in either FEI or SCM mode, XCLK is turned off. Any peripherals which can use XCLK
as a clock source must not do so when the ICG is in FEI or SCM mode.
7.4
7.4.1
The section is intended to give some basic direction on which configuration a user would want to select
when initializing the ICG. For some applications, the serial communication link may dictate the accuracy
of the clock reference. For other applications, lowest power consumption may be the chief clock
consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in
choosing which is best for any application.
The following sections contain initialization examples for various configurations.
Important configuration information is repeated here for reference sake.
110
1. The IRG typically consumes 100 µA. The FLL and DCO typically consumes 0.5 to 2.5 mA, depending upon output frequency.
For minimum power consumption and minimum jitter, choose N and R to be as small as possible.
Bypassed
Engaged
FLL
FLL
Initialization/Application Information
Introduction
Hexadecimal values designated by a preceding $, binary values designated
by a preceding %, and decimal values have no preceding character.
FEI
4 MHz < f
Medium power (will be less than FEE if oscillator
range = high)
Good clock accuracy (After IRG is trimmed)
Lowest system cost (no external components
required)
IRG is on. DCO is on.
SCM
This mode is mainly provided for quick and reliable
system startup.
3 MHz < f
3 MHz < f
Medium power
Poor accuracy.
IRG is off. DCO is on and open loop.
Clock Reference Source = Internal
Bus
Bus
Bus
< 20 MHz.
< 5 MHz (default).
< 20 MHz (via filter bits).
Table 7-4. ICG Configuration Consideration
(1)
MC9S08GB/GT Data Sheet, Rev. 2.3
NOTE
FEE
4 MHz < f
Medium power (will be less than FEI if oscillator
range = low)
High clock accuracy
Medium/High system cost (crystal, resonator or
external clock source required)
IRG is off. DCO is on.
FBE
f
used.
Lowest power
Highest clock accuracy
Medium/High system cost (Crystal, resonator or
external clock source required)
IRG is off. DCO is off.
Bus
range <= 8 MHz when crystal or resonator is
Clock Reference Source = External
Bus
< 20 MHz
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