M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 54

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Memory
4.6.1
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
DIVLD — Divisor Loaded Status Flag
PRDIV8 — Prescale (Divide) FLASH Clock by 8
DIV5:DIV0 — Divisor for FLASH Clock Divider
Table 4-6
54
When set, this read-only status flag indicates that the FCDIV register has been written since reset.
Reset clears this bit and the first write to this register causes this bit to become set regardless of the
data written.
The FLASH clock divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1)
by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the internal FLASH
clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/erase
timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 µs to
6.7 µs. The automated programming logic uses an integer number of these pulses to complete an erase
or program operation.
1 = FCDIV has been written since reset; erase and program operations enabled for FLASH.
0 = FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 = Clock input to the FLASH clock divider is the bus rate clock divided by 8.
0 = Clock input to the FLASH clock divider is the bus rate clock.
shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
FLASH Clock Divider Register (FCDIV)
Reset:
Read:
Write:
if PRDIV8 = 1 — f
if PRDIV8 = 0 — f
Figure 4-4. FLASH Clock Divider Register (FCDIV)
DIVLD
Bit 7
0
= Unimplemented or Reserved
PRDIV8
MC9S08GB/GT Data Sheet, Rev. 2.3
6
0
FCLK
FCLK
= f
= f
Bus
DIV5
5
0
Bus
÷ (8 × ([DIV5:DIV0] + 1))
÷ ([DIV5:DIV0] + 1)
DIV4
4
0
DIV3
3
0
DIV2
2
0
DIV1
Freescale Semiconductor
1
0
DIV0
Bit 0
0
Eqn. 4-1
Eqn. 4-2