M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 70

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Resets, Interrupts, and System Configuration
POR — Power-On Reset
PIN — External Reset Pin
COP — Computer Operating Properly (COP) Watchdog
ILOP — Illegal Opcode
ICG — Internal Clock Generation Module Reset
70
1
Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping
up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
Reset was caused by an active-low level on the external reset pin.
Reset was caused by the COP watchdog timer timing out. This reset source may be blocked by
COPE = 0.
Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction
is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
Reset was caused by an ICG module reset.
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset will be cleared.
1 = POR caused reset.
0 = Reset not caused by POR.
1 = Reset came from external reset pin.
0 = Reset not caused by external reset pin.
1 = Reset caused by COP timeout.
0 = Reset not caused by COP timeout.
1 = Reset caused by an illegal opcode.
0 = Reset not caused by an illegal opcode.
1 = Reset caused by ICG module.
0 = Reset not caused by ICG module.
Low-voltage reset:
Power-on reset:
Any other reset:
Read:
Write:
U = Unaffected by reset
POR
Bit 7
U
1
0
Figure 5-3. System Reset Status (SRS)
Writing any value to SIMRS address clears COP watchdog timer.
MC9S08GB/GT Data Sheet, Rev. 2.3
PIN
6
0
0
1
COP
(1)
5
0
0
ILOP
(1)
4
0
0
3
0
0
0
0
ICG
(1)
2
0
0
LVD
Freescale Semiconductor
1
1
1
0
Bit 0
0
0
0
0