M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 37

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After the device enters background debug mode, all
background commands are available. The table below summarizes the behavior of the MCU in stop when
entry into the background debug mode is enabled.
1
3.6.5
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will
instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is
enabled.
1
3.6.6
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Mode,”
behavior in stop modes.
Freescale Semiconductor
Mode
Stop3
Mode
Stop3
Either ATD stop mode or power-down mode depending on the state of ATDPU.
Either ATD stop mode or power-down mode depending on the state of ATDPU.
Section 3.6.2, “Stop2
Don’t
Don’t
PDC
PDC
care
care
LVD Enabled in Stop Mode
On-Chip Peripheral Modules in Stop Modes
PPDC
PPDC
Don’t
Don’t
care
care
CPU, Digital
Peripherals,
CPU, Digital
Peripherals,
Standby
Standby
FLASH
FLASH
Mode,” and
Table 3-2. BDM Enabled Stop Mode Behavior
Table 3-3. LVD Enabled Stop Mode Behavior
MC9S08GB/GT Data Sheet, Rev. 2.3
Standby
Standby
RAM
RAM
Section 3.6.3, “Stop3
Standby
Active
ICG
ICG
Disabled
Disabled
ATD
ATD
Mode,” for specific information on system
1
1
Regulator
Regulator
Active
Active
Section 3.6.1, “Stop1
I/O Pins
I/O Pins
States
States
held
held
Optionally on
Optionally on
Stop Modes
RTI
RTI
37