ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 43

BOARD DAUGHTER FOR ADSP-21262

ADZS-21262-1-EZEXT

Manufacturer Part Number
ADZS-21262-1-EZEXT
Description
BOARD DAUGHTER FOR ADSP-21262
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADZS-21262-1-EZEXT

Accessory Type
DSP
Silicon Manufacturer
Analog Devices
Core Architecture
SHARC
Features
Expansion Interface, High Speed Converter (HSC) Interface
Kit Contents
Board Docs
Silicon Family Name
SHARC
Silicon Core Number
ADSP-21262
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADSP-21262
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
JTAG Test Access Port and Emulation
Table 41. JTAG Test Access Port and Emulation
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = ADDR15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0.
System Outputs = MISO, MOSI, SPICLK, DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
1
1
2
OUTPUTS
SYSTEM
SYSTEM
INPUTS
TCK
TMS
TDO
TDI
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
t
DTDO
t
TCK
Figure 36. IEEE 1149.1 JTAG Test Access Port
t
Rev. G | Page 43 of 56 | March 2011
t
DSYS
SSYS
t
STAP
t
HTAP
t
HSYS
Min
t
5
6
7
18
4 × t
CK
CK
Max
7
t
CK
÷ 2 + 7
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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