ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 3

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

GENERAL DESCRIPTION
The ADSP-2136x SHARC
SHARC family of DSPs that feature Analog Devices, Inc., Super
Harvard Architecture. The processor is source code-compatible
with the ADSP-2126x and ADSP-2116x DSPs, as well as with
first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. The ADSP-2136x are
32-/40-bit floating-point processors optimized for high
performance automotive audio applications. They contain a
large on-chip SRAM and ROM, multiple internal buses to elim-
inate I/O bottlenecks, and an innovative digital audio interface
(DAI).
As shown in the functional block diagram
ADSP-2136x uses two computational units to deliver a signifi-
cant performance increase over the previous SHARC processors
on a range of signal processing algorithms. With its SIMD com-
putational hardware, the ADSP-2136x can perform two
GFLOPS running at 333 MHz.
Table 2. ADSP-2136x Family Features
1
2
The diagram
up the ADSP-2136x processors. The core clock domain contains
the following features:
Feature
RAM
ROM
Audio Decoders in ROM
Pulse-Width Modulation
S/PDIF
DTCP
SRC SNR Performance
Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay,
The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices
speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system
configurations. Please visit www.analog.com for complete information.
sales office for more information.
• Two processing elements, each of which comprises an
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
• One periodic interval timer with pinout
• On-chip SRAM (3M bit)
• On-chip mask-programmable ROM (4M bit)
• JTAG test access port for emulation and boundary scan.
ALU, multiplier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
The JTAG provides software debug through user break-
points, which allow flexible exception handling.
2
on Page 1
shows the two clock domains that make
1
®
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
processor is a member of the SIMD
ADSP-21362
3M bit
4M bit
No
Yes
Yes
Yes
–128 dB
on Page
1, the
Rev. G | Page 3 of 56 | March 2011
ADSP-21363
3M bit
4M bit
No
Yes
No
No
No SRC
Table 1
Table 2
Table 1. Benchmarks (at 333 MHz)
1
The diagram
features:
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
Divide (y/x)
Inverse Square Root
Assumes two files in multichannel SIMD mode.
[3×3] × [3×1]
[4×4] × [4×1]
• I/O processor that handles 32-bit DMA for the peripherals
• Six full duplex serial ports
• Two SPI-compatible interface ports—primary on dedi-
• 8-bit or 16-bit parallel port that supports interfaces to off-
• Digital audio interface that includes two precision clock
cated pins, secondary on DAI pins
chip memory peripherals
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, 8-channel asynchronous sample rate
converter, DTCP cipher, six serial ports, eight serial inter-
faces, a 20-bit parallel input port, 10 interrupts, six flag
outputs, six flag inputs, three timers, and a flexible signal
routing unit (SRU)
3M bit
4M bit
No
Yes
Yes
No
ADSP-21364
–140 dB
shows performance benchmarks for these devices.
shows the features of the individual product offerings.
on Page 1
1
1
also shows the following architectural
ADSP-21365
3M bit
4M bit
Yes
Yes
Yes
Yes
–128 dB
ADSP-21366
3M bit
4M bit
Yes
Yes
Yes
No
–128 dB
Speed
(at 333 MHz)
1.5 ns
6.0 ns
13.5 ns
23.9 ns
10.5 ns
16.3 ns