ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 27

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 23. 16-Bit Memory Write Cycle
1
2
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
D = (the value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
F = 7 × t
t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
This parameter is only available when in EMPP = 0 mode.
ALEW
ADAS
ALERW
RWALE
WRH
ADAH
WW
DWS
DWH
PCLK
2
PCLK
1
= (peripheral) clock period = 2 × t
1
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be 9 × t
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
AD15–0 Data Setup Before WR High
AD15–0 Data Hold After WR High
AD15–0
ALE
WR
RD
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.
t
t
ALEW
ADAS
VALID ADDRESS
CCLK
t
Figure 20. Write Cycle for 16-Bit Memory Timing
ADAH
t
ALEHZ
t
ALERW
Rev. G | Page 27 of 56 | March 2011
t
t
0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.
RW
VALID DATA
DRS
PCLK
.
t
DRH
t
RRH
Min
2 × t
t
2 × t
H + 0.5
F + H + t
t
D – F – 2.0
D – F + t
H
PCLK
PCLK
K and B Grade
PCLK
PCLK
– 2.5
– 2.3
PCLK
PCLK
PCLK
VALID DATA
– 2.0
– 3.8
.
– 4.0
– 2.3
t
RWALE
t
RDDRV
Min
2 × t
t
2 × t
H + 0.5
F + H + t
t
D – F – 2.0
D – F + t
H
PCLK
PCLK
PCLK
PCLK
– 2.5
– 2.3
ADDRESS
VALID
Y Grade
PCLK
PCLK
– 2.0
– 3.8
– 4.0
– 2.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns