ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 17

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Power-Up Sequencing
The timing requirements for processor startup are given in
Table
supply comes up after V
Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
depending on the design of the power supply subsystem.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
default states at all I/O pins.
maximum.
10. Note that during power-up, when the V
DDINT
1
/V
DDEXT
CLK_CFG1–0
RESETOUT
assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,
RESET
V
V
CLKIN
DDINT
DDEXT
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
DDEXT
DDINT
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SRST
On Before V
, a leakage current of the order of
specification in
t
RSTVDD
DDEXT
DDINT
DDINT
Table
/V
/V
t
12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles
DDEXT
IVDDEVDD
DDINT
DDEXT
Rev. G | Page 17 of 56 | March 2011
Valid
Figure 6. Power-Up Sequencing
On
power
t
CLKVDD
t
PLLRST
t
CLKRST
three-state leakage current pull-up, pull-down, may be observed
on any pin, even if that is an input only (for example the RESET
pin) until the V
Min
0
–50
0
10
20
4096t
2
DDINT
CK
t
CORERST
+ 2 t
rail has powered up.
CCLK
3, 4
Max
+200
200
Unit
ns
ms
ms
μs
μs