ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 28

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync (FS) delay and frame sync setup and
hold, 2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Table 24. Serial Ports—External Clock
1
2
Table 25. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Referenced to the sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DFSIR
HOFSIR
DDTI
HDTI
SCLKIW
1
1
1
2
1
1
2
2
1
1
2
2
2
1
2
2
2
2
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode)
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
Rev. G | Page 28 of 56 | March 2011
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Min
2.5
2.5
2.5
2.5
(t
t
2
2
PCLK
PCLK
× 4
× 4) ÷ 2 – 0.5
K and B Grade
Min
7
2.5
7
2.5
–1.0
–1.0
2 × t
PCLK
K and B Grade
– 2 2 × t
Max
9.5
9.5
Max
3
8
3
PCLK
+ 2 2 × t
Max
11
11
Y Grade
Max
3.5
9.5
4.0
Y Grade
PCLK
+ 2 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns