PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 9

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PIC16F684-I/SLG

Manufacturer Part Number
PIC16F684-I/SLG
Description
pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
Manufacturer
Microchip
Datasheet
2.0
2.1
The PIC16F684 has a 13-bit program counter capable
of addressing an 8k x 14 program memory space. Only
the first 2k x 14 (0000h-07FFh) for the PIC16F684 is
physically implemented. Accessing a location above
these boundaries will cause a wrap around within the
first 2k x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
 2004 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
On-chip Program
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
PC<12:0>
Memory
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F684
13
000h
0004
0005
07FFh
0800h
1FFFh
Preliminary
2.2
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose Regis-
ters (GPR) and the Special Function Registers (SFR).
The Special Function Registers are located in the first
32 locations of each bank. Register locations 20h-7Fh
in Bank 0 and A0h-BFh in Bank 1 are General Purpose
Registers, implemented as static RAM. Register
locations F0h-FFh in Bank 1 point to addresses
70h-7Fh in Bank 0. All other RAM is unimplemented
and returns ‘0’ when read. RP0 (Status<5>) is the bank
select bit.
RP0 = 0:
RP0 = 1:
Note:
Data Memory Organization
The IRP and RP1 bits Status<7:6> are
reserved
maintained as ‘0’s.
Bank 0 is selected
Bank 1 is selected
and
PIC16F684
should
DS41202C-page 7
always
be

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