PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 15

• Manufacturer Part Number: PIC16F684-I/SLG
• Description: pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
• Manufacturer: Microchip

2.2.2.3
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTA change and
external RA2/INT pin interrupts.
REGISTER 2-3:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON Register
INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
RAIE: PORTA Change Interrupt Enable bit
1 = Enables the PORTA change interrupt
0 = Disables the PORTA change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
RAIF: PORTA Change Interrupt Flag bit
1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)
0 = None of the PORTA <5:0> pins have changed state
Legend:
R = Readable bit
-n = Value at POR
R/W-0
Note 1: IOCA register must also be enabled.
GIE
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should
be initialized before clearing T0IF bit.
R/W-0
PEIE
R/W-0
T0IE
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-0
INTE
(2)
Note:
(1)
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RAIE
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
R/W-0
T0IF
PIC16F684
x = Bit is unknown
R/W-0
INTF
DS41202C-page 13
R/W-0
RAIF
bit 0