PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 17

• Manufacturer Part Number: PIC16F684-I/SLG
• Description: pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
• Manufacturer: Microchip

2.2.2.5
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR1 Register
PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
C2IF: Comparator 2 Interrupt Flag bit
1 = Comparator 2 output has changed (must be cleared in software)
0 = Comparator 2 output has not changed
C1IF: Comparator 1 Interrupt Flag bit
1 = Comparator 1 output has changed (must be cleared in software)
0 = Comparator 1 output has not changed
OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match has not occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 register overflowed (must be cleared in software)
0 = Timer1 has not overflowed
Legend:
R = Readable bit
-n = Value at POR
R/W-0
EEIF
R/W-0
ADIF
CCP1IF
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-0
C2IF
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
C1IF
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
OSFIF
R/W-0
PIC16F684
x = Bit is unknown
TMR2IF
R/W-0
DS41202C-page 15
TMR1IF
R/W-0
bit 0