PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 104

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PIC16F684-I/SLG

Manufacturer Part Number
PIC16F684-I/SLG
Description
pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
Manufacturer
Microchip
Datasheet
PIC16F684
12.4.2
An overflow (FFh
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
FIGURE 12-7:
DS41202C-page 102
TMR0 INTERRUPT
IOC-RA0
IOC-RA1
IOC-RA2
IOC-RA3
IOC-RA4
IOC-RA5
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
IOCA0
IOCA1
IOCA2
IOCA3
IOCA4
IOCA5
OSFIF
OSFIE
ADIF
ADIE
EEIE
C1IF
C1IE
C2IF
C2IE
EEIF
00h) in the TMR0 register will set
by
INTERRUPT LOGIC
setting/clearing
T0IE
Preliminary
RAIE
INTF
INTE
RAIF
PEIE
T0IF
T0IE
GIE
12.4.3
An input change on PORTA change sets the RAIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA register.
Note:
PORTA INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
Wake-up (If in Sleep mode)
 2004 Microchip Technology Inc.
Interrupt to CPU

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