PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 87

• Manufacturer Part Number: PIC16F684-I/SLG
• Description: pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
• Manufacturer: Microchip

11.3.6
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on,
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current
(shoot-through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-bridge Output mode, a digitally program-
mable dead band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal transi-
tion from the non-active state to the active state. See
Figure 11-6 for illustration. The lower seven bits of the
PWM1CON register (Register 11-2) sets the delay
period in terms of microcontroller instruction cycles
(T
REGISTER 11-2:
 2004 Microchip Technology Inc.
CY
or 4 T
OSC
bit 7
bit 6-0
PROGRAMMABLE DEAD BAND
DELAY
).
PWM1CON – PWM CONFIGURATION REGISTER (ADDRESS: 16
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM.
PDC<6:0>: PWM Delay Count bits
Number of F
transition active, and the actual time it transitions active.
Legend:
R = Readable bit
-n = Value at POR
PRSEN
R/W-0
goes away; the PWM restarts automatically.
OSC
R/W-0
PDC6
/4 (4*T
OSC
R/W-0
PDC5
) cycles between the scheduled time when a PWM signal should
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-0
PDC4
11.3.7
When the ECCP is programmed for any of the
enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
A shutdown event can be caused by either of the two
comparators or the INT pin (or any combination of
these three sources). The comparators may be used to
monitor a voltage input proportional to a current being
monitored in the bridge circuit. If the voltage exceeds a
threshold, the comparator switches state and triggers a
shutdown. Alternatively, a digital signal on the INT pin
can also trigger a shutdown. The auto-shutdown
feature can be disabled by not selecting any
auto-shutdown sources. The auto-shutdown sources to
be used are selected using the ECCPAS<2:0> bits
(ECCPAS<6:4>).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states, spec-
ified by the PSSAC<1:0> and PSSBD<1:0> bits
(ECCPAS<3:0>). Each pin pair (P1A/P1C and
P1B/P1D) may be set to drive high, drive low, or be
tri-stated
(ECCPAS<7>) is also set to hold the enhanced PWM
outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If Auto-restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If Auto-restarts are enabled, the
ECCPASE bit is automatically cleared when the cause
of
Section 11.3.7.1 “Auto-shutdown and Auto-restart”
for more information.
the
R/W-0
PDC3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENHANCED PWM
AUTO-SHUTDOWN
(not
auto-shutdown
driving).
R/W-0
PDC2
PIC16F684
The
has
x = Bit is unknown
R/W-0
PDC1
h
)
DS41202C-page 85
ECCPASE
cleared.
R/W-0
PDC0
bit 0
See
bit