PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 47

• Manufacturer Part Number: PIC16F684-I/SLG
• Description: pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
• Manufacturer: Microchip

5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 5-1:
 2004 Microchip Technology Inc.
T0CKI
SWDTEN
Note:
pin
WDTE
(= F
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register.
CLKOUT
OSC
31 kHz
INTRC
T0SE
TIMER0 MODULE
Timer0 Operation
/4)
Additional information on the Timer0
module is available in the “PICmicro
Mid-Range
Manual” (DS33023).
Watchdog
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Timer
T0CS
MCU
0
1
Family
PSA
Prescaler
0
1
16-bit
Reference
16
Prescaler
WDTPS<3:0>
8-bit
Preliminary
®
8
PS<2:0>
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin RA2/T0CKI. The incrementing edge is determined
by
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
5.2
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit (INTCON<2>). The interrupt
can be masked by clearing the T0IE bit (INTCON<5>).
The T0IF bit must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The Timer0 interrupt cannot wake the
processor from Sleep since the timer is shut off during
Sleep.
Note:
the
Timer0 Interrupt
Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
”PICmicro
Reference Manual” (DS33023).
PSA
PSA
source
1
0
1
0
SYNC 2
Cycles
Time-out
®
edge
WDT
Mid-Range
PIC16F684
(T0SE)
Data Bus
Set Flag bit T0IF
DS41202C-page 45
8
TMR0
on Overflow
MCU
control
Family
bit