PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 81

• Manufacturer Part Number: PIC16F684-I/SLG
• Description: pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
• Manufacturer: Microchip

11.3.2
A PWM output (Figure 11-4 and Figure 11-5) has a time
base (period) and a time that the output is active (duty
cycle). The PWM period is specified by writing to the
PR2 register. The PWM period can be calculated using
the following formula:
EQUATION 11-1:
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The appropriate PWM pin toggles. In Dual PWM
• The PWM duty cycle is latched from CCPR1L into
11.3.3
The PWM duty cycle is specified by writing to the
CCPR1L
(CCP1CON<5:4>) bits. Up to 10 bits of resolution is
available. The CCPR1L contains the eight MSbs and
the DC1B<1:0> contains the two LSbs. CCPR1L and
DC1B<1:0> can be written to at any time. In PWM
mode, CCPR1H is a read-only register. This 10-bit
value is represented by CCPR1L (CCP1CON<5:4>).
TABLE 11-4:
 2004 Microchip Technology Inc.
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
Note 1:
mode, this occurs after the dead band delay
expires (exception: if PWM duty cycle = 0%, the
pin will not be set)
CCPR1H
Note:
PWM period
PWM Frequency
Changing duty cycle will cause a glitch.
PWM PERIOD
The Timer2 postscaler (see Section 7.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
register
(TMR2 prescale value)
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
=
and
PR2
+
to
1
1.22 kHz
4 T
0xFF
the
16
10
OSC
(1)
DC1B<1:0>
4.88 kHz
0xFF
Preliminary
10
4
(1)
19.53 kHz
The following equation is used to calculate the PWM
duty cycle in time:
EQUATION 11-2:
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the appropriate PWM pin is
toggled. In Dual PWM mode, the pin will be toggled
after the dead band time has expired.
The polarity (active-high or active-low) and mode of the
signal
(CCP1CON<7:6>)
(CCP1CON<3:0>) bits.
The maximum PWM resolution for a given PWM
frequency is given by the formula:
EQUATION 11-3:
All control registers are double buffered and are loaded
at the beginning of a new PWM cycle (the period
boundary when Timer2 resets) in order to prevent
glitches on any of the outputs. The exception is the
PWM delay register, which is loaded at either the duty
cycle boundary or the period boundary (whichever
comes first). Because of the buffering, the module
waits until the timer resets, instead of starting immedi-
ately. This means that enhanced PWM waveforms do
not exactly match the standard PWM waveforms, but
are instead offset by one full instruction cycle (4 T
PWM duty cycle
0xFF
Note:
Resolution
10
1
T
are
OSC
If the PWM duty cycle value is longer than
the PWM period, the assigned PWM pin(s)
will remain unchanged.
78.12 kHz
=
configured
0x3F
log
-------------------------------------------------------------------------- - bits
=
1
8
(TMR2 prescale value)


OSC
CCPR1L:CCP1CON<5:4>
------------------------------------------------------------ -
F
PWM
= 20 MHz)
PIC16F684
and
log
156.3 kHz
TMR2 Prescaler
F
by
0x1F
OSC
2
1
7
DS41202C-page 79
the
CCP1M<3:0>
208.3 kHz
P1M<1:0>


0x17
6.6
1
OSC
).