PIC16F684-I/SLG Microchip, PIC16F684-I/SLG Datasheet - Page 83

• Manufacturer Part Number: PIC16F684-I/SLG
• Description: pic, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
• Manufacturer: Microchip

11.3.4
In the Half-bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the RC5/CCP1/P1A pin, while the com-
plementary PWM output signal is output on the
RC4/C2OUT/P1B pin (Figure 11-6). This mode can be
used for half-bridge applications, as shown in
Figure 11-7, or for full-bridge applications, where four
power switches are being modulated with two PWM
signals.
In Half-bridge Output mode, the programmable dead
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC<6:0> (PWM1CON<6:0>) sets the number of
instruction cycles before the output is driven active. If
the value is greater than the duty cycle, the corre-
sponding output remains inactive during the entire
cycle. See Section 11.3.6 “Programmable Dead
Band Delay” for more details of the dead band delay
operations.
FIGURE 11-7:
 2004 Microchip Technology Inc.
Standard Half-bridge Circuit (“Push-Pull”)
Half-bridge Output Driving a Full-bridge Circuit
HALF-BRIDGE MODE
PIC16F684
EXAMPLES OF HALF-BRIDGE APPLICATIONS
P1A
P1B
PIC16F684
P1A
P1B
FET
Driver
FET
Driver
Preliminary
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the PORTC<5:4> data latches, the TRISC<5:4> bits
must be cleared to configure P1A and P1B as outputs.
FIGURE 11-6:
P1A
P1B
td = Dead Band Delay
Load
Note 1: At this time, the TMR2 register is equal to the
V+
V-
(2)
(2)
V+
V-
2: Output signals are shown as active-high.
(1)
td
Duty Cycle
PR2 register.
Load
Period
td
FET
Driver
FET
Driver
HALF-BRIDGE PWM
OUTPUT
+
V
-
+
V
-
PIC16F684
(1)
Period
DS41202C-page 81
(1)