zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 97

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via
User_Port_Enable register.
The User Defined Range provides a range of logical port numbers with the same priority level. Programming is
similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need
to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit
is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the
upper limit and more than the lower limit will use the priority specified in RPRIORITY.
14.9.40.1
USER_PORT_0 - I
USER_PORT_1 - I
USER_PORT_2 - I
USER_PORT_3 - I
USER_PORT_4 - I
USER_PORT_5 - I
USER_PORT_6 - I
USER_PORT_7 - I
Accessed by CPU, serial interface and I
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
14.9.40.2
I
Accessed by CPU, serial interface and I
The chip allows the CPU to define the priority.
2
C Address h0E6, CPU Address 590
Bits [3:0]:
Bits [7:4]:
USER_PORT0_(0~7) – User Define Logical Port (0~7)
USER_PORT_[1:0]_PRIORITY - U
7
Priority 1
7
7
2
2
2
2
2
2
2
2
C Address h0D6 + 0DE; CPU Address 580(Low) + 581(high)
C Address h0D7 + 0DF; CPU Address 582 + 583
C Address h0D8 + 0E0; CPU Address 584 + 585
C Address h0D9 + 0E1; CPU Address 586 + 587
C Address h0DA + 0E2; CPU Address 588 + 589
C Address h0DB + 0E3; CPU Address 58A + 58B
C Address h0DC + 0E4; CPU Address 58C + 58D
C Address h0DD + 0E5; CPU Address 58E + 58F
TCP/UDP Logic Port High
TCP/UDP Logic Port Low
Priority setting, transmission + dropping, for logic port 0
Priority setting, transmission + dropping, for logic port 1 (Default 00)
5
4
Drop
2
2
3
Priority 0
C (R/W)
C (R/W)
Zarlink Semiconductor Inc.
ZL50418
1
SER
97
Drop
0
D
0
0
EFINE
L
OGIC
P
ORT
1
AND
0 P
RIORITY
Data Sheet