zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 13

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

1.0
1.1
The FDB interface supports pipelined synchronous burst SRAM (SBRAM) memory at 100 MHz. To ensure a
non-blocking switch, two memory domains are required. Each domain has a 64 bit wide memory bus. At 100 MHz,
the aggregate memory bandwidth is 12.8 Gbps, which is enough to support 16 10/100 Mbps and 2 Gigabit ports at
full wire speed switching.
The Switching Database is also located in the external SRAM; it is used for storing MAC addresses and their
physical port number. It is duplicated and stored in both memory domains. Therefore, when the system updates the
contents of the switching database it has to write the entry to both domains at the same time.
1.2
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between
the Frame Engine (FE) and the external physical device (PHY).
The ZL50418 GMAC implements both GMII and MII interface, which offers a simple migration from 10/100 to 1 G.
The GMAC of the ZL50418 meets the IEEE 802.3Z specification. It is able to operate in 10 M/100 M either Half or
Full Duplex mode with a back pressure/flow control mechanism or in 1 G Full duplex mode with flow control
mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. PHY
addresses for GMAC are 01h and 02h.
For fiber optics media, the ZL50418 implements the Physical Code Sublayer (PCS) interface. The PCS includes an
8B10B encoder and decoder, auto-negotiation, and Ten Bit Interface (TBI)
1.3
For the ZL50418, the 1000BASE-X PCS Interface is designed internally and may be utilized in the absence of a
GMII. The PCS incorporates all the functions required by the GMII to include encoding (decoding) 8B GMII data to
(from) 8B/10B TBI format for PHY communication and generating Collision Detect (COL) signals for half-duplex
mode. It also manages the Auto negotiation process by informing the management entity that the PHY is ready for
communications. The on-chip TBI may be disabled if TBI exists within the Gigabit PHY. The TBI interface provides
a uniform interface for all 1000 Mbps PHY implementations.
The PCS comprises the PCS Transmit, Synchronization, PCS Receive and Auto negotiation processes for
1000BASE-X.
The PCS Transmit process sends the TBI signals TXD [9:0] to the physical medium and generates the GMII
Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission.
Additionally, the Transmit process generates an internal “transmitting” flag and monitors Auto negotiation to
determine whether to transmit data or to reconfigure the link.
The PCS Synchronization process determines whether or not the receive channel is operational.
The PCS Receive process generates RXD [7:0] on the GMII from the TBI data [9:0] and the internal “receiving” flag
for use by the Transmit processes.
The PCS Auto negotiation process allows the ZL50418 to exchange configuration information between two devices
that share a link segment and to automatically configure the link for the appropriate speed of operation for both
devices.
Frame Data Buffer (FDB) Interfaces
GMII/PCS MAC Module (GMAC)
Physical Coding Sublayer (PCS) Interface
Block Functionality
Zarlink Semiconductor Inc.
ZL50418
13
Data Sheet